net/txgbe: add Rx and Tx init

[dpdk.git] / drivers / net / hns3 / hns3_ethdev.h

diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index f170df9..da8aead 100644 (file)
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -64,6 +64,8 @@
 #define HNS3_HIP08_MIN_TX_PKT_LEN      33
 #define HNS3_HIP09_MIN_TX_PKT_LEN      9
 
+#define HNS3_BITS_PER_BYTE     8
+
 #define HNS3_4_TCS                     4
 #define HNS3_8_TCS                     8
 
@@ -132,9 +134,9 @@ enum hns3_fc_status {
 };
 
 struct hns3_tc_queue_info {
-       uint8_t tqp_offset;     /* TQP offset from base TQP */
-       uint8_t tqp_count;      /* Total TQPs */
-       uint8_t tc;             /* TC index */
+       uint16_t tqp_offset;    /* TQP offset from base TQP */
+       uint16_t tqp_count;     /* Total TQPs */
+       uint8_t tc;             /* TC index */
        bool enable;            /* If this TC is enable or not */
 };
 
@@ -275,6 +277,13 @@ enum hns3_reset_level {
         * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
         * of the reset level and the one defined in kernel driver should be
         * same.
+        *
+        * According to the protocol of PCIe, FLR to a PF resets the PF state as
+        * well as the SR-IOV extended capability including VF Enable which
+        * means that VFs no longer exist.
+        *
+        * In PF FLR, the register state of VF is not reliable, VF's driver
+        * should not access the registers of the VF device.
         */
        HNS3_VF_FULL_RESET = 3,
        HNS3_FLR_RESET,     /* A VF perform FLR reset */
@@ -652,11 +661,35 @@ struct hns3_ptype_table {
        uint32_t ol4table[HNS3_OL4TBL_NUM];
 };
 
+#define HNS3_FIXED_MAX_TQP_NUM_MODE            0
+#define HNS3_FLEX_MAX_TQP_NUM_MODE             1
+
 struct hns3_pf {
        struct hns3_adapter *adapter;
        bool is_main_pf;
        uint16_t func_num; /* num functions of this pf, include pf and vfs */
 
+       /*
+        * tqp_config mode
+        * tqp_config_mode value range:
+        *      HNS3_FIXED_MAX_TQP_NUM_MODE,
+        *      HNS3_FLEX_MAX_TQP_NUM_MODE
+        *
+        * - HNS3_FIXED_MAX_TQP_NUM_MODE
+        *   There is a limitation on the number of pf interrupts available for
+        *   on some versions of network engines. In this case, the maximum
+        *   queue number of pf can not be greater than the interrupt number,
+        *   such as pf of network engine with revision_id 0x21. So the maximum
+        *   number of queues must be fixed.
+        *
+        * - HNS3_FLEX_MAX_TQP_NUM_MODE
+        *   In this mode, the maximum queue number of pf has not any constraint
+        *   and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
+        *   in the config file. Users can modify the macro according to their
+        *   own application scenarios, which is more flexible to use.
+        */
+       uint8_t tqp_config_mode;
+
        uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
        uint32_t tx_buf_size; /* Tx buffer size for each TC */
        uint32_t dv_buf_size; /* Dv buffer size for each TC */
@@ -679,6 +712,7 @@ struct hns3_pf {
        struct hns3_err_msix_intr_stats abn_int_stats;
 
        bool support_sfp_query;
+       uint32_t fec_mode; /* current FEC mode for ethdev */
 
        struct hns3_vtag_cfg vtag_config;
        LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
@@ -712,7 +746,7 @@ struct hns3_adapter {
 #define HNS3_DEV_SUPPORT_DCB_B                 0x0
 #define HNS3_DEV_SUPPORT_COPPER_B              0x1
 #define HNS3_DEV_SUPPORT_UDP_GSO_B             0x2
-#define HNS3_DEV_SUPPORT_ADQ_B                 0x3
+#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B     0x3
 #define HNS3_DEV_SUPPORT_PTP_B                 0x4
 #define HNS3_DEV_SUPPORT_TX_PUSH_B             0x5
 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B          0x6
@@ -729,9 +763,9 @@ struct hns3_adapter {
 #define hns3_dev_udp_gso_supported(hw) \
        hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
 
-/* Support Application Device Queue */
-#define hns3_dev_adq_supported(hw) \
-       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
+/* Support the queue region action rule of flow directory */
+#define hns3_dev_fd_queue_region_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
 
 /* Support PTP timestamp offload */
 #define hns3_dev_ptp_supported(hw) \
@@ -783,6 +817,8 @@ struct hns3_adapter {
 
 #define BIT(nr) (1UL << (nr))
 
+#define BIT_ULL(x) (1ULL << (x))
+
 #define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
 #define GENMASK(h, l) \
        (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))