#define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
#define HNS3_DEFAULT_MTU 1500UL
#define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
-#define HNS3_MIN_PKT_SIZE 60
+#define HNS3_HIP08_MIN_TX_PKT_LEN 33
+#define HNS3_HIP09_MIN_TX_PKT_LEN 9
#define HNS3_4_TCS 4
#define HNS3_8_TCS 8
struct hns3_wait_data *wait_data;
};
+#define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
+#define HNS3_INTR_MAPPING_VEC_ALL 1
+
+#define HNS3_INTR_COALESCE_NON_QL 0
+#define HNS3_INTR_COALESCE_QL 1
+
+#define HNS3_INTR_COALESCE_GL_UINT_2US 0
+#define HNS3_INTR_COALESCE_GL_UINT_1US 1
+
+struct hns3_queue_intr {
+ /*
+ * interrupt mapping mode.
+ * value range:
+ * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
+ *
+ * - HNS3_INTR_MAPPING_VEC_RSV_ONE
+ * For some versions of hardware network engine, because of the
+ * hardware constraint, we need implement clearing the mapping
+ * relationship configurations by binding all queues to the last
+ * interrupt vector and reserving the last interrupt vector. This
+ * method results in a decrease of the maximum queues when upper
+ * applications call the rte_eth_dev_configure API function to
+ * enable Rx interrupt.
+ *
+ * - HNS3_INTR_MAPPING_VEC_ALL
+ * PMD driver can map/unmmap all interrupt vectors with queues When
+ * Rx interrupt in enabled.
+ */
+ uint8_t mapping_mode;
+ /*
+ * interrupt coalesce mode.
+ * value range:
+ * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
+ *
+ * - HNS3_INTR_COALESCE_NON_QL
+ * For some versions of hardware network engine, hardware doesn't
+ * support QL(quanity limiter) algorithm for interrupt coalesce
+ * of queue's interrupt.
+ *
+ * - HNS3_INTR_COALESCE_QL
+ * In this mode, hardware support QL(quanity limiter) algorithm for
+ * interrupt coalesce of queue's interrupt.
+ */
+ uint8_t coalesce_mode;
+ /*
+ * The unit of GL(gap limiter) configuration for interrupt coalesce of
+ * queue's interrupt.
+ * value range:
+ * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
+ */
+ uint8_t gl_unit;
+};
+
struct hns3_hw {
struct rte_eth_dev_data *data;
void *io_base;
uint16_t tqps_num; /* num task queue pairs of this function */
uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
uint16_t rss_size_max; /* HW defined max RSS task queue */
+ uint16_t rx_buf_len; /* hold min hardware rx buf len */
uint16_t num_tx_desc; /* desc num of per tx queue */
uint16_t num_rx_desc; /* desc num of per rx queue */
+ uint32_t mng_entry_num; /* number of manager table entry */
+ uint32_t mac_entry_num; /* number of mac-vlan table entry */
struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
int mc_addrs_num; /* Multicast mac addresses number */
/* The configuration info of RSS */
struct hns3_rss_conf rss_info;
bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
+ uint16_t rss_ind_tbl_size;
+ uint16_t rss_key_size;
uint8_t num_tc; /* Total number of enabled TCs */
uint8_t hw_tc_map;
uint16_t tx_qnum_per_tc; /* TX queue number per TC */
uint32_t capability;
+ uint32_t max_tm_rate;
+ /*
+ * The minimum length of the packet supported by hardware in the Tx
+ * direction.
+ */
+ uint32_t min_tx_pkt_len;
+
+ struct hns3_queue_intr intr;
+
+ uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
struct hns3_port_base_vlan_config port_base_vlan_cfg;
/*
#define HNS3_FLAG_VNET_BASE_SCH_MODE 2
struct hns3_err_msix_intr_stats {
- uint64_t mac_afifo_tnl_intr_cnt;
- uint64_t ppu_mpf_abnormal_intr_st2_cnt;
- uint64_t ssu_port_based_pf_intr_cnt;
- uint64_t ppp_pf_abnormal_intr_cnt;
- uint64_t ppu_pf_abnormal_intr_cnt;
+ uint64_t mac_afifo_tnl_int_cnt;
+ uint64_t ppu_mpf_abn_int_st2_msix_cnt;
+ uint64_t ssu_port_based_pf_int_cnt;
+ uint64_t ppp_pf_abnormal_int_cnt;
+ uint64_t ppu_pf_abnormal_int_msix_cnt;
+
+ uint64_t imp_tcm_ecc_int_cnt;
+ uint64_t cmdq_mem_ecc_int_cnt;
+ uint64_t imp_rd_poison_int_cnt;
+ uint64_t tqp_int_ecc_int_cnt;
+ uint64_t msix_ecc_int_cnt;
+ uint64_t ssu_ecc_multi_bit_int_0_cnt;
+ uint64_t ssu_ecc_multi_bit_int_1_cnt;
+ uint64_t ssu_common_ecc_int_cnt;
+ uint64_t igu_int_cnt;
+ uint64_t ppp_mpf_abnormal_int_st1_cnt;
+ uint64_t ppp_mpf_abnormal_int_st3_cnt;
+ uint64_t ppu_mpf_abnormal_int_st1_cnt;
+ uint64_t ppu_mpf_abn_int_st2_ras_cnt;
+ uint64_t ppu_mpf_abnormal_int_st3_cnt;
+ uint64_t tm_sch_int_cnt;
+ uint64_t qcn_fifo_int_cnt;
+ uint64_t qcn_ecc_int_cnt;
+ uint64_t ncsi_ecc_int_cnt;
+ uint64_t ssu_port_based_err_int_cnt;
+ uint64_t ssu_fifo_overflow_int_cnt;
+ uint64_t ssu_ets_tcg_int_cnt;
+ uint64_t igu_egu_tnl_int_cnt;
+ uint64_t ppu_pf_abnormal_int_ras_cnt;
};
/* vlan entry information. */
/* Key string for IPC. */
#define HNS3_MP_NAME "net_hns3_mp"
+#define HNS3_L2TBL_NUM 4
+#define HNS3_L3TBL_NUM 16
+#define HNS3_L4TBL_NUM 16
+#define HNS3_OL3TBL_NUM 16
+#define HNS3_OL4TBL_NUM 16
+
+struct hns3_ptype_table {
+ uint32_t l2table[HNS3_L2TBL_NUM];
+ uint32_t l3table[HNS3_L3TBL_NUM];
+ uint32_t l4table[HNS3_L4TBL_NUM];
+ uint32_t inner_l2table[HNS3_L2TBL_NUM];
+ uint32_t inner_l3table[HNS3_L3TBL_NUM];
+ uint32_t inner_l4table[HNS3_L4TBL_NUM];
+ uint32_t ol3table[HNS3_OL3TBL_NUM];
+ uint32_t ol4table[HNS3_OL4TBL_NUM];
+};
+
struct hns3_pf {
struct hns3_adapter *adapter;
bool is_main_pf;
struct hns3_pf pf;
struct hns3_vf vf;
};
+
+ bool rx_simple_allowed;
+ bool rx_vec_allowed;
+ bool tx_simple_allowed;
+ bool tx_vec_allowed;
+
+ struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define HNS3_DEV_SUPPORT_COPPER_B 0x1
+#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
+#define HNS3_DEV_SUPPORT_ADQ_B 0x3
+#define HNS3_DEV_SUPPORT_PTP_B 0x4
+#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
+#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
+#define HNS3_DEV_SUPPORT_STASH_B 0x7
#define hns3_dev_dcb_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
+/* Support copper media type */
#define hns3_dev_copper_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
+/* Support UDP GSO offload */
+#define hns3_dev_udp_gso_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
+
+/* Support Application Device Queue */
+#define hns3_dev_adq_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
+
+/* Support PTP timestamp offload */
+#define hns3_dev_ptp_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
+
+#define hns3_dev_tx_push_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
+
+/* Support to Independently enable/disable/reset Tx or Rx queues */
+#define hns3_dev_indep_txrx_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
+
+#define hns3_dev_stash_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
+
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-#define max_t(type, x, y) ({ \
- type __max1 = (x); \
- type __max2 = (y); \
- __max1 > __max2 ? __max1 : __max2; })
-
+/*
+ * Because hardware always access register in little-endian mode based on hns3
+ * network engine, so driver should also call rte_cpu_to_le_32 to convert data
+ * in little-endian mode before writing register and call rte_le_to_cpu_32 to
+ * convert data after reading from register.
+ *
+ * Here the driver encapsulates the data conversion operation in the register
+ * read/write operation function as below:
+ * hns3_write_reg
+ * hns3_write_reg_opt
+ * hns3_read_reg
+ * Therefore, when calling these functions, conversion is not required again.
+ */
static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
{
- rte_write32(value, (volatile void *)((char *)base + reg));
+ rte_write32(rte_cpu_to_le_32(value),
+ (volatile void *)((char *)base + reg));
+}
+
+/*
+ * The optimized function for writing registers used in the '.rx_pkt_burst' and
+ * '.tx_pkt_burst' ops implementation function.
+ */
+static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
+{
+ rte_io_wmb();
+ rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
}
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
{
- return rte_read32((volatile void *)((char *)base + reg));
+ uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
+ return rte_le_to_cpu_32(read_val);
}
#define hns3_write_dev(a, reg, value) \
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