#include <sys/time.h>
#include <rte_alarm.h>
+#include "hns3_cmd.h"
+#include "hns3_mbx.h"
+#include "hns3_rss.h"
+#include "hns3_fdir.h"
+#include "hns3_stats.h"
+
/* Vendor ID */
#define PCI_VENDOR_ID_HUAWEI 0x19e5
#define HNS3_DEV_ID_25GE_RDMA 0xA222
#define HNS3_DEV_ID_50GE_RDMA 0xA224
#define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
+#define HNS3_DEV_ID_200G_RDMA 0xA228
#define HNS3_DEV_ID_100G_VF 0xA22E
#define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
+/* PCI Config offsets */
+#define HNS3_PCI_REVISION_ID 0x08
+#define HNS3_PCI_REVISION_ID_LEN 1
+
+#define PCI_REVISION_ID_HIP08_B 0x21
+#define PCI_REVISION_ID_HIP09_A 0x30
+
+#define HNS3_PF_FUNC_ID 0
+#define HNS3_1ST_VF_FUNC_ID 1
+
#define HNS3_UC_MACADDR_NUM 128
#define HNS3_VF_UC_MACADDR_NUM 48
#define HNS3_MC_MACADDR_NUM 128
#define HNS3_MAX_BD_SIZE 65535
-#define HNS3_MAX_TX_BD_PER_PKT 8
+#define HNS3_MAX_NON_TSO_BD_PER_PKT 8
+#define HNS3_MAX_TSO_BD_PER_PKT 63
#define HNS3_MAX_FRAME_LEN 9728
-#define HNS3_MIN_FRAME_LEN 64
#define HNS3_VLAN_TAG_SIZE 4
#define HNS3_DEFAULT_RX_BUF_LEN 2048
+#define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
+#define HNS3_MAX_TSO_HDR_SIZE 512
+#define HNS3_MAX_TSO_HDR_BD_NUM 3
+#define HNS3_MAX_LRO_SIZE 64512
#define HNS3_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
#define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
#define HNS3_DEFAULT_MTU 1500UL
#define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
+#define HNS3_HIP08_MIN_TX_PKT_LEN 33
+#define HNS3_HIP09_MIN_TX_PKT_LEN 9
#define HNS3_4_TCS 4
#define HNS3_8_TCS 8
-#define HNS3_MAX_TC_NUM 8
#define HNS3_MAX_PF_NUM 8
#define HNS3_UMV_TBL_SIZE 3072
uint32_t link_speed; /* ETH_SPEED_NUM_ */
};
+struct hns3_fake_queue_data {
+ void **rx_queues; /* Array of pointers to fake RX queues. */
+ void **tx_queues; /* Array of pointers to fake TX queues. */
+ uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
+ uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
+};
+
+#define HNS3_PORT_BASE_VLAN_DISABLE 0
+#define HNS3_PORT_BASE_VLAN_ENABLE 1
+struct hns3_port_base_vlan_config {
+ uint16_t state;
+ uint16_t pvid;
+};
/* Primary process maintains driver state in main thread.
*
uint64_t merge_cnt; /* Total merged in high reset times */
};
-struct hns3_hw;
-struct hns3_adapter;
-
typedef bool (*check_completion_func)(struct hns3_hw *hw);
struct hns3_wait_data {
struct hns3_wait_data *wait_data;
};
+#define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
+#define HNS3_INTR_MAPPING_VEC_ALL 1
+
+#define HNS3_INTR_COALESCE_NON_QL 0
+#define HNS3_INTR_COALESCE_QL 1
+
+#define HNS3_INTR_COALESCE_GL_UINT_2US 0
+#define HNS3_INTR_COALESCE_GL_UINT_1US 1
+
+struct hns3_queue_intr {
+ /*
+ * interrupt mapping mode.
+ * value range:
+ * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
+ *
+ * - HNS3_INTR_MAPPING_VEC_RSV_ONE
+ * For some versions of hardware network engine, because of the
+ * hardware constraint, we need implement clearing the mapping
+ * relationship configurations by binding all queues to the last
+ * interrupt vector and reserving the last interrupt vector. This
+ * method results in a decrease of the maximum queues when upper
+ * applications call the rte_eth_dev_configure API function to
+ * enable Rx interrupt.
+ *
+ * - HNS3_INTR_MAPPING_VEC_ALL
+ * PMD driver can map/unmmap all interrupt vectors with queues When
+ * Rx interrupt in enabled.
+ */
+ uint8_t mapping_mode;
+ /*
+ * interrupt coalesce mode.
+ * value range:
+ * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
+ *
+ * - HNS3_INTR_COALESCE_NON_QL
+ * For some versions of hardware network engine, hardware doesn't
+ * support QL(quanity limiter) algorithm for interrupt coalesce
+ * of queue's interrupt.
+ *
+ * - HNS3_INTR_COALESCE_QL
+ * In this mode, hardware support QL(quanity limiter) algorithm for
+ * interrupt coalesce of queue's interrupt.
+ */
+ uint8_t coalesce_mode;
+ /*
+ * The unit of GL(gap limiter) configuration for interrupt coalesce of
+ * queue's interrupt.
+ * value range:
+ * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
+ */
+ uint8_t gl_unit;
+};
+
struct hns3_hw {
struct rte_eth_dev_data *data;
void *io_base;
+ uint8_t revision; /* PCI revision, low byte of class word */
+ struct hns3_cmq cmq;
+ struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
+ struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
+ pthread_t irq_thread_id;
struct hns3_mac mac;
unsigned int secondary_cnt; /* Number of secondary processes init'd. */
+ struct hns3_tqp_stats tqp_stats;
+ /* Include Mac stats | Rx stats | Tx stats */
+ struct hns3_mac_stats mac_stats;
uint32_t fw_version;
uint16_t num_msi;
uint16_t total_tqps_num; /* total task queue pairs of this PF */
uint16_t tqps_num; /* num task queue pairs of this function */
+ uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
uint16_t rss_size_max; /* HW defined max RSS task queue */
- uint16_t rx_buf_len;
+ uint16_t rx_buf_len; /* hold min hardware rx buf len */
uint16_t num_tx_desc; /* desc num of per tx queue */
uint16_t num_rx_desc; /* desc num of per rx queue */
+ uint32_t mng_entry_num; /* number of manager table entry */
+ uint32_t mac_entry_num; /* number of mac-vlan table entry */
struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
int mc_addrs_num; /* Multicast mac addresses number */
+ /* The configuration info of RSS */
+ struct hns3_rss_conf rss_info;
+ bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
+ uint16_t rss_ind_tbl_size;
+ uint16_t rss_key_size;
+
uint8_t num_tc; /* Total number of enabled TCs */
uint8_t hw_tc_map;
enum hns3_fc_mode current_mode;
struct hns3_dcb_info dcb_info;
enum hns3_fc_status current_fc_status; /* current flow control status */
struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
- uint16_t alloc_tqps;
- uint16_t alloc_rss_size; /* Queue number per TC */
+ uint16_t used_rx_queues;
+ uint16_t used_tx_queues;
+
+ /* Config max queue numbers between rx and tx queues from user */
+ uint16_t cfg_max_queues;
+ struct hns3_fake_queue_data fkq_data; /* fake queue data */
+ uint16_t alloc_rss_size; /* RX queue number per TC */
+ uint16_t tx_qnum_per_tc; /* TX queue number per TC */
- uint32_t flag;
+ uint32_t capability;
+ uint32_t max_tm_rate;
+ /*
+ * The minimum length of the packet supported by hardware in the Tx
+ * direction.
+ */
+ uint32_t min_tx_pkt_len;
+
+ struct hns3_queue_intr intr;
+
+ uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
+
+ struct hns3_port_base_vlan_config port_base_vlan_cfg;
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
#define HNS3_FLAG_VNET_BASE_SCH_MODE 2
struct hns3_err_msix_intr_stats {
- uint64_t mac_afifo_tnl_intr_cnt;
- uint64_t ppu_mpf_abnormal_intr_st2_cnt;
- uint64_t ssu_port_based_pf_intr_cnt;
- uint64_t ppp_pf_abnormal_intr_cnt;
- uint64_t ppu_pf_abnormal_intr_cnt;
+ uint64_t mac_afifo_tnl_int_cnt;
+ uint64_t ppu_mpf_abn_int_st2_msix_cnt;
+ uint64_t ssu_port_based_pf_int_cnt;
+ uint64_t ppp_pf_abnormal_int_cnt;
+ uint64_t ppu_pf_abnormal_int_msix_cnt;
+
+ uint64_t imp_tcm_ecc_int_cnt;
+ uint64_t cmdq_mem_ecc_int_cnt;
+ uint64_t imp_rd_poison_int_cnt;
+ uint64_t tqp_int_ecc_int_cnt;
+ uint64_t msix_ecc_int_cnt;
+ uint64_t ssu_ecc_multi_bit_int_0_cnt;
+ uint64_t ssu_ecc_multi_bit_int_1_cnt;
+ uint64_t ssu_common_ecc_int_cnt;
+ uint64_t igu_int_cnt;
+ uint64_t ppp_mpf_abnormal_int_st1_cnt;
+ uint64_t ppp_mpf_abnormal_int_st3_cnt;
+ uint64_t ppu_mpf_abnormal_int_st1_cnt;
+ uint64_t ppu_mpf_abn_int_st2_ras_cnt;
+ uint64_t ppu_mpf_abnormal_int_st3_cnt;
+ uint64_t tm_sch_int_cnt;
+ uint64_t qcn_fifo_int_cnt;
+ uint64_t qcn_ecc_int_cnt;
+ uint64_t ncsi_ecc_int_cnt;
+ uint64_t ssu_port_based_err_int_cnt;
+ uint64_t ssu_fifo_overflow_int_cnt;
+ uint64_t ssu_ets_tcg_int_cnt;
+ uint64_t igu_egu_tnl_int_cnt;
+ uint64_t ppu_pf_abnormal_int_ras_cnt;
};
/* vlan entry information. */
uint16_t vlan_id;
};
-struct hns3_port_base_vlan_config {
- uint16_t state;
- uint16_t pvid;
-};
-
/* Vlan tag configuration for RX direction */
struct hns3_rx_vtag_cfg {
uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
/* Key string for IPC. */
#define HNS3_MP_NAME "net_hns3_mp"
+#define HNS3_L2TBL_NUM 4
+#define HNS3_L3TBL_NUM 16
+#define HNS3_L4TBL_NUM 16
+#define HNS3_OL3TBL_NUM 16
+#define HNS3_OL4TBL_NUM 16
+
+struct hns3_ptype_table {
+ uint32_t l2table[HNS3_L2TBL_NUM];
+ uint32_t l3table[HNS3_L3TBL_NUM];
+ uint32_t l4table[HNS3_L4TBL_NUM];
+ uint32_t inner_l2table[HNS3_L2TBL_NUM];
+ uint32_t inner_l3table[HNS3_L3TBL_NUM];
+ uint32_t inner_l4table[HNS3_L4TBL_NUM];
+ uint32_t ol3table[HNS3_OL3TBL_NUM];
+ uint32_t ol4table[HNS3_OL4TBL_NUM];
+};
+
struct hns3_pf {
struct hns3_adapter *adapter;
bool is_main_pf;
+ uint16_t func_num; /* num functions of this pf, include pf and vfs */
uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
uint32_t tx_buf_size; /* Tx buffer size for each TC */
bool support_sfp_query;
struct hns3_vtag_cfg vtag_config;
- struct hns3_port_base_vlan_config port_base_vlan_cfg;
LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
+
+ struct hns3_fdir_info fdir; /* flow director info */
+ LIST_HEAD(counters, hns3_flow_counter) flow_counters;
};
struct hns3_vf {
struct hns3_pf pf;
struct hns3_vf vf;
};
+
+ bool rx_simple_allowed;
+ bool rx_vec_allowed;
+ bool tx_simple_allowed;
+ bool tx_vec_allowed;
+
+ struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
#define HNS3_DEV_SUPPORT_DCB_B 0x0
+#define HNS3_DEV_SUPPORT_COPPER_B 0x1
+#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
+#define HNS3_DEV_SUPPORT_ADQ_B 0x3
+#define HNS3_DEV_SUPPORT_PTP_B 0x4
+#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
+#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
+#define HNS3_DEV_SUPPORT_STASH_B 0x7
#define hns3_dev_dcb_supported(hw) \
- hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
+
+/* Support copper media type */
+#define hns3_dev_copper_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
+
+/* Support UDP GSO offload */
+#define hns3_dev_udp_gso_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
+
+/* Support Application Device Queue */
+#define hns3_dev_adq_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
+
+/* Support PTP timestamp offload */
+#define hns3_dev_ptp_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
+
+#define hns3_dev_tx_push_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
+
+/* Support to Independently enable/disable/reset Tx or Rx queues */
+#define hns3_dev_indep_txrx_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
+
+#define hns3_dev_stash_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-#define max_t(type, x, y) ({ \
- type __max1 = (x); \
- type __max2 = (y); \
- __max1 > __max2 ? __max1 : __max2; })
-
+/*
+ * Because hardware always access register in little-endian mode based on hns3
+ * network engine, so driver should also call rte_cpu_to_le_32 to convert data
+ * in little-endian mode before writing register and call rte_le_to_cpu_32 to
+ * convert data after reading from register.
+ *
+ * Here the driver encapsulates the data conversion operation in the register
+ * read/write operation function as below:
+ * hns3_write_reg
+ * hns3_write_reg_opt
+ * hns3_read_reg
+ * Therefore, when calling these functions, conversion is not required again.
+ */
static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
{
- rte_write32(value, (volatile void *)((char *)base + reg));
+ rte_write32(rte_cpu_to_le_32(value),
+ (volatile void *)((char *)base + reg));
+}
+
+/*
+ * The optimized function for writing registers used in the '.rx_pkt_burst' and
+ * '.tx_pkt_burst' ops implementation function.
+ */
+static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
+{
+ rte_io_wmb();
+ rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
}
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
{
- return rte_read32((volatile void *)((char *)base + reg));
+ uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
+ return rte_le_to_cpu_32(read_val);
}
#define hns3_write_dev(a, reg, value) \
return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
}
+int hns3_buffer_alloc(struct hns3_hw *hw);
+int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
+ enum rte_filter_type filter_type,
+ enum rte_filter_op filter_op, void *arg);
+bool hns3_is_reset_pending(struct hns3_adapter *hns);
+bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
+void hns3_update_link_status(struct hns3_hw *hw);
+
+static inline bool
+is_reset_pending(struct hns3_adapter *hns)
+{
+ bool ret;
+ if (hns->is_vf)
+ ret = hns3vf_is_reset_pending(hns);
+ else
+ ret = hns3_is_reset_pending(hns);
+ return ret;
+}
+
+static inline uint64_t
+hns3_txvlan_cap_get(struct hns3_hw *hw)
+{
+ if (hw->port_base_vlan_cfg.state)
+ return DEV_TX_OFFLOAD_VLAN_INSERT;
+ else
+ return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
+}
+
#endif /* _HNS3_ETHDEV_H_ */
git.droids-corp.org / dpdk.git / blobdiff