#include <rte_alarm.h>
#include <ethdev_pci.h>
#include <rte_io.h>
-#include <rte_pci.h>
#include <rte_vfio.h>
#include "hns3_ethdev.h"
/* When RSS is not configured, redirect the packet queue 0 */
if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
- hw->rss_dis_flag = false;
rss_conf = conf->rx_adv_conf.rss_conf;
ret = hns3_dev_rss_hash_update(dev, &rss_conf);
if (ret)
static int
hns3vf_get_capability(struct hns3_hw *hw)
{
- struct rte_pci_device *pci_dev;
- struct rte_eth_dev *eth_dev;
- uint8_t revision;
int ret;
- eth_dev = &rte_eth_devices[hw->data->port_id];
- pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
-
- /* Get PCI revision id */
- ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
- HNS3_PCI_REVISION_ID);
- if (ret != HNS3_PCI_REVISION_ID_LEN) {
- PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
- ret);
- return -EIO;
- }
- hw->revision = revision;
+ ret = hns3_get_pci_revision_id(hw, &hw->revision);
+ if (ret)
+ return ret;
- if (revision < PCI_REVISION_ID_HIP09_A) {
+ if (hw->revision < PCI_REVISION_ID_HIP09_A) {
hns3vf_set_default_dev_specifications(hw);
hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
return hns3vf_check_tqp_info(hw);
}
-static int
-hns3vf_get_queue_depth(struct hns3_hw *hw)
-{
-#define HNS3VF_TQPS_DEPTH_INFO_LEN 4
- uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
- int ret;
-
- ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
- resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
- if (ret) {
- PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
- ret);
- return ret;
- }
-
- memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
- memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
-
- return 0;
-}
-
static void
hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
{
int ret;
hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
- hw->rss_dis_flag = false;
/* Get device capability */
ret = hns3vf_get_capability(hw);
if (ret)
return ret;
- /* Get queue depth info from PF */
- ret = hns3vf_get_queue_depth(hw);
- if (ret)
- return ret;
-
/* Get user defined VF MAC addr from PF */
ret = hns3vf_get_host_mac_addr(hw);
if (ret)
return hns3vf_get_port_base_vlan_filter_state(hw);
}
-static int
-hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
- uint16_t nb_tx_q)
-{
- struct hns3_hw *hw = &hns->hw;
-
- return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
-}
-
static void
hns3vf_request_link_info(struct hns3_hw *hw)
{
* Before querying the link status, check whether there is a reset
* pending, and if so, abandon the query.
*/
- if (!hns3vf_is_reset_pending(hns))
+ if (!hns3vf_is_reset_pending(hns)) {
hns3vf_request_link_info(hw);
- else
+ hns3_update_hw_stats(hw);
+ } else {
hns3_warn(hw, "Cancel the query when reset is pending");
+ }
rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
eth_dev);
goto err_get_config;
}
- ret = hns3_tqp_stats_init(hw);
+ ret = hns3_stats_init(hw);
if (ret)
goto err_get_config;
- /* Hardware statistics of imissed registers cleared. */
- ret = hns3_update_imissed_stats(hw, true);
- if (ret) {
- hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
- goto err_set_tc_queue;
- }
-
- ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
+ ret = hns3_queue_to_tc_mapping(hw, hw->tqps_num, hw->tqps_num);
if (ret) {
PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
goto err_set_tc_queue;
return 0;
err_set_tc_queue:
- hns3_tqp_stats_uninit(hw);
+ hns3_stats_uninit(hw);
err_get_config:
hns3vf_disable_irq0(hw);
(void)hns3vf_set_alive(hw, false);
(void)hns3vf_set_promisc_mode(hw, false, false, false);
hns3_flow_uninit(eth_dev);
- hns3_tqp_stats_uninit(hw);
+ hns3_stats_uninit(hw);
hns3vf_disable_irq0(hw);
rte_intr_disable(pci_dev->intr_handle);
hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
uint16_t nb_tx_q = hw->data->nb_tx_queues;
int ret;
- ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
+ ret = hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
if (ret)
return ret;
static int
hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
{
+#define HNS3_WAIT_PF_RESET_READY_TIME 5
struct hns3_hw *hw = &hns->hw;
struct hns3_wait_data *wait_data = hw->reset.wait_data;
struct timeval tv;
return 0;
wait_data->check_completion = NULL;
- wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
+ wait_data->interval = HNS3_WAIT_PF_RESET_READY_TIME *
+ MSEC_PER_SEC * USEC_PER_MSEC;
wait_data->count = 1;
wait_data->result = HNS3_WAIT_REQUEST;
rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
wait_data);
- hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
+ hns3_warn(hw, "hardware is ready, delay %d sec for PF reset complete",
+ HNS3_WAIT_PF_RESET_READY_TIME);
return -EAGAIN;
} else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
hns3_clock_gettime(&tv);
.get_reg = hns3_get_regs,
.dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
.tx_done_cleanup = hns3_tx_done_cleanup,
+ .eth_dev_priv_dump = hns3_eth_dev_priv_dump,
};
static const struct hns3_reset_ops hns3vf_reset_ops = {
PMD_INIT_FUNC_TRACE();
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
- __atomic_fetch_sub(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
hns3_mp_uninit(eth_dev);
return 0;
}