net/mlx5: fix flow age event triggering

[dpdk.git] / drivers / net / hns3 / hns3_ethdev_vf.c

diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c
index 061ba27..9a85e97 100644 (file)
--- a/drivers/net/hns3/hns3_ethdev_vf.c
+++ b/drivers/net/hns3/hns3_ethdev_vf.c
@@ -857,11 +857,6 @@ hns3vf_dev_configure(struct rte_eth_dev *dev)
        if (ret)
                goto cfg_err;
 
-       hns->rx_simple_allowed = true;
-       hns->rx_vec_allowed = true;
-       hns->tx_simple_allowed = true;
-       hns->tx_vec_allowed = true;
-
        hns3_init_rx_ptype_tble(dev);
 
        hw->adapter_state = HNS3_NIC_CONFIGURED;
@@ -1032,6 +1027,11 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
        info->reta_size = hw->rss_ind_tbl_size;
        info->hash_key_size = HNS3_RSS_KEY_SIZE;
        info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
+
+       info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
+       info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
+       info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
+       info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
        info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
        info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 
@@ -1516,7 +1516,6 @@ static void
 hns3vf_request_link_info(struct hns3_hw *hw)
 {
        struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
-       uint8_t resp_msg;
        bool send_req;
        int ret;
 
@@ -1529,7 +1528,7 @@ hns3vf_request_link_info(struct hns3_hw *hw)
                return;
 
        ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
-                               &resp_msg, sizeof(resp_msg));
+                               NULL, 0);
        if (ret) {
                hns3_err(hw, "failed to fetch link status, ret = %d", ret);
                return;
@@ -1761,11 +1760,10 @@ hns3vf_keep_alive_handler(void *param)
        struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
        struct hns3_adapter *hns = eth_dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
-       uint8_t respmsg;
        int ret;
 
        ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
-                               false, &respmsg, sizeof(uint8_t));
+                               false, NULL, 0);
        if (ret)
                hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
                         ret);
@@ -2188,8 +2186,11 @@ hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
                                      HNS3_FW_VERSION_BYTE1_S),
                       hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
                                      HNS3_FW_VERSION_BYTE0_S));
+       if (ret < 0)
+               return -EINVAL;
+
        ret += 1; /* add the size of '\0' */
-       if (fw_size < (uint32_t)ret)
+       if (fw_size < (size_t)ret)
                return ret;
        else
                return 0;
@@ -2470,7 +2471,8 @@ hns3vf_is_reset_pending(struct hns3_adapter *hns)
        /* Check the registers to confirm whether there is reset pending */
        hns3vf_check_event_cause(hns, NULL);
        reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
-       if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
+       if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
+           hw->reset.level < reset) {
                hns3_warn(hw, "High level reset %d is pending", reset);
                return true;
        }
@@ -2508,7 +2510,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
                hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
                return -EAGAIN;
        } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
-               gettimeofday(&tv, NULL);
+               hns3_clock_gettime(&tv);
                hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
                          tv.tv_sec, tv.tv_usec);
                return -ETIME;
@@ -2518,7 +2520,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
        wait_data->hns = hns;
        wait_data->check_completion = is_vf_reset_done;
        wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
-                                     HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
+                               HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
        wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
        wait_data->count = HNS3VF_RESET_WAIT_CNT;
        wait_data->result = HNS3_WAIT_REQUEST;
@@ -2773,14 +2775,13 @@ hns3vf_reset_service(void *param)
         */
        reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
        if (reset_level != HNS3_NONE_RESET) {
-               gettimeofday(&tv_start, NULL);
+               hns3_clock_gettime(&tv_start);
                hns3_reset_process(hns, reset_level);
-               gettimeofday(&tv, NULL);
+               hns3_clock_gettime(&tv);
                timersub(&tv, &tv_start, &tv_delta);
-               msec = tv_delta.tv_sec * MSEC_PER_SEC +
-                      tv_delta.tv_usec / USEC_PER_MSEC;
+               msec = hns3_clock_calctime_ms(&tv_delta);
                if (msec > HNS3_RESET_PROCESS_MS)
-                       hns3_err(hw, "%d handle long time delta %" PRIx64
+                       hns3_err(hw, "%d handle long time delta %" PRIu64
                                 " ms time=%ld.%.6ld",
                                 hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
        }
@@ -2917,8 +2918,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev)
                return -ENOMEM;
        }
 
-       /* initialize flow filter lists */
-       hns3_filterlist_init(eth_dev);
+       hns3_flow_init(eth_dev);
 
        hns3_set_rxtx_function(eth_dev);
        eth_dev->dev_ops = &hns3vf_eth_dev_ops;
@@ -3079,4 +3079,5 @@ RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
                HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
-               HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
+               HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
+               HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");