common/sfc_efx/base: implement Tx control path for Riverhead

[dpdk.git] / drivers / net / hns3 / hns3_fdir.c

diff --git a/drivers/net/hns3/hns3_fdir.c b/drivers/net/hns3/hns3_fdir.c
index 5729923..65ab19d 100644 (file)
--- a/drivers/net/hns3/hns3_fdir.c
+++ b/drivers/net/hns3/hns3_fdir.c
@@ -29,20 +29,23 @@
 
 #define HNS3_FD_AD_DATA_S              32
 #define HNS3_FD_AD_DROP_B              0
-#define HNS3_FD_AD_DIRECT_QID_B        1
+#define HNS3_FD_AD_DIRECT_QID_B                1
 #define HNS3_FD_AD_QID_S               2
-#define HNS3_FD_AD_QID_M               GENMASK(12, 2)
+#define HNS3_FD_AD_QID_M               GENMASK(11, 2)
 #define HNS3_FD_AD_USE_COUNTER_B       12
 #define HNS3_FD_AD_COUNTER_NUM_S       13
-#define HNS3_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
+#define HNS3_FD_AD_COUNTER_NUM_M       GENMASK(19, 13)
 #define HNS3_FD_AD_NXT_STEP_B          20
 #define HNS3_FD_AD_NXT_KEY_S           21
-#define HNS3_FD_AD_NXT_KEY_M           GENMASK(26, 21)
-#define HNS3_FD_AD_WR_RULE_ID_B        0
+#define HNS3_FD_AD_NXT_KEY_M           GENMASK(25, 21)
+#define HNS3_FD_AD_WR_RULE_ID_B                0
 #define HNS3_FD_AD_RULE_ID_S           1
-#define HNS3_FD_AD_RULE_ID_M           GENMASK(13, 1)
-#define HNS3_FD_AD_COUNTER_HIGH_BIT     7
-#define HNS3_FD_AD_COUNTER_HIGH_BIT_B   26
+#define HNS3_FD_AD_RULE_ID_M           GENMASK(12, 1)
+#define HNS3_FD_AD_QUEUE_REGION_EN_B   16
+#define HNS3_FD_AD_QUEUE_REGION_SIZE_S 17
+#define HNS3_FD_AD_QUEUE_REGION_SIZE_M GENMASK(20, 17)
+#define HNS3_FD_AD_COUNTER_HIGH_BIT    7
+#define HNS3_FD_AD_COUNTER_HIGH_BIT_B  26
 
 enum HNS3_PORT_TYPE {
        HOST_PORT,
@@ -426,13 +429,19 @@ static int hns3_fd_ad_config(struct hns3_hw *hw, int loc,
                     action->write_rule_id_to_bd);
        hns3_set_field(ad_data, HNS3_FD_AD_RULE_ID_M, HNS3_FD_AD_RULE_ID_S,
                       action->rule_id);
+       if (action->nb_queues > 1) {
+               hns3_set_bit(ad_data, HNS3_FD_AD_QUEUE_REGION_EN_B, 1);
+               hns3_set_field(ad_data, HNS3_FD_AD_QUEUE_REGION_SIZE_M,
+                              HNS3_FD_AD_QUEUE_REGION_SIZE_S,
+                              rte_log2_u32(action->nb_queues));
+       }
        /* set extend bit if counter_id is in [128 ~ 255] */
        if (action->counter_id & BIT(HNS3_FD_AD_COUNTER_HIGH_BIT))
                hns3_set_bit(ad_data, HNS3_FD_AD_COUNTER_HIGH_BIT_B, 1);
        ad_data <<= HNS3_FD_AD_DATA_S;
        hns3_set_bit(ad_data, HNS3_FD_AD_DROP_B, action->drop_packet);
-       hns3_set_bit(ad_data, HNS3_FD_AD_DIRECT_QID_B,
-                    action->forward_to_direct_queue);
+       if (action->nb_queues == 1)
+               hns3_set_bit(ad_data, HNS3_FD_AD_DIRECT_QID_B, 1);
        hns3_set_field(ad_data, HNS3_FD_AD_QID_M, HNS3_FD_AD_QID_S,
                       action->queue_id);
        hns3_set_bit(ad_data, HNS3_FD_AD_USE_COUNTER_B, action->use_counter);
@@ -440,7 +449,7 @@ static int hns3_fd_ad_config(struct hns3_hw *hw, int loc,
                       HNS3_FD_AD_COUNTER_NUM_S, action->counter_id);
        hns3_set_bit(ad_data, HNS3_FD_AD_NXT_STEP_B, action->use_next_stage);
        hns3_set_field(ad_data, HNS3_FD_AD_NXT_KEY_M, HNS3_FD_AD_NXT_KEY_S,
-                      action->counter_id);
+                      action->next_input_key);
 
        req->ad_data = rte_cpu_to_le_64(ad_data);
        ret = hns3_cmd_send(hw, &desc, 1);
@@ -752,12 +761,12 @@ static int hns3_config_action(struct hns3_hw *hw, struct hns3_fdir_rule *rule)
 
        if (rule->action == HNS3_FD_ACTION_DROP_PACKET) {
                ad_data.drop_packet = true;
-               ad_data.forward_to_direct_queue = false;
                ad_data.queue_id = 0;
+               ad_data.nb_queues = 0;
        } else {
                ad_data.drop_packet = false;
-               ad_data.forward_to_direct_queue = true;
                ad_data.queue_id = rule->queue_id;
+               ad_data.nb_queues = rule->nb_queues;
        }
 
        if (unlikely(rule->flags & HNS3_RULE_FLAG_COUNTER)) {