/* configure TM QCN hw errors */
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, false);
- if (en)
+ desc.data[0] = rte_cpu_to_le_32(HNS3_TM_QCN_ERR_INT_TYPE);
+ if (en) {
+ desc.data[0] |= rte_cpu_to_le_32(HNS3_TM_QCN_FIFO_INT_EN);
desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
+ }
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
{
struct hns3_hw *hw = &hns->hw;
- if (hns3_dev_ras_imp_supported(hw)) {
+ if (hns3_dev_get_support(hw, RAS_IMP)) {
hns3_handle_hw_error_v2(hw);
hns3_schedule_reset(hns);
} else {
static bool
hns3_reset_err_handle(struct hns3_adapter *hns)
{
-#define MAX_RESET_FAIL_CNT 5
+#define MAX_RESET_FAIL_CNT 30
struct hns3_hw *hw = &hns->hw;
static int
hns3_reset_post(struct hns3_adapter *hns)
{
-#define TIMEOUT_RETRIES_CNT 5
+#define TIMEOUT_RETRIES_CNT 30
struct hns3_hw *hw = &hns->hw;
struct timeval tv_delta;
struct timeval tv;