/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
*/
#ifndef _HNS3_MBX_H_
#define _HNS3_MBX_H_
-#define HNS3_MBX_VF_MSG_DATA_NUM 16
-
enum HNS3_MBX_OPCODE {
HNS3_MBX_RESET = 0x01, /* (VF -> PF) assert reset */
HNS3_MBX_ASSERTING_RESET, /* (PF -> VF) PF is asserting reset */
HNS3_MBX_SET_MTU, /* (VF -> PF) set mtu */
HNS3_MBX_GET_QID_IN_PF, /* (VF -> PF) get queue id in pf */
+ HNS3_MBX_PUSH_VLAN_INFO = 34, /* (PF -> VF) push port base vlan */
+
+ HNS3_MBX_PUSH_PROMISC_INFO = 36, /* (PF -> VF) push vf promisc info */
+
HNS3_MBX_HANDLE_VF_TBL = 38, /* (VF -> PF) store/clear hw cfg tbl */
+ HNS3_MBX_GET_RING_VECTOR_MAP, /* (VF -> PF) get ring-to-vector map */
+ HNS3_MBX_PUSH_LINK_STATUS = 201, /* (IMP -> PF) get port link status */
};
/* below are per-VF mac-vlan subcodes */
HNS3_MBX_VLAN_FILTER = 0, /* set vlan filter */
HNS3_MBX_VLAN_TX_OFF_CFG, /* set tx side vlan offload */
HNS3_MBX_VLAN_RX_OFF_CFG, /* set rx side vlan offload */
+ HNS3_MBX_GET_PORT_BASE_VLAN_STATE = 4, /* get port based vlan state */
};
enum hns3_mbx_tbl_cfg_subcode {
HNS3_MBX_VPORT_LIST_CLEAR = 0,
};
+enum hns3_mbx_link_fail_subcode {
+ HNS3_MBX_LF_NORMAL = 0,
+ HNS3_MBX_LF_REF_CLOCK_LOST,
+ HNS3_MBX_LF_XSFP_TX_DISABLE,
+ HNS3_MBX_LF_XSFP_ABSENT,
+};
+
#define HNS3_MBX_MAX_MSG_SIZE 16
#define HNS3_MBX_MAX_RESP_DATA_SIZE 8
-#define HNS3_MBX_RING_MAP_BASIC_MSG_NUM 3
-#define HNS3_MBX_RING_NODE_VARIABLE_NUM 3
+
+enum {
+ HNS3_MBX_RESP_MATCHING_SCHEME_OF_ORIGINAL = 0,
+ HNS3_MBX_RESP_MATCHING_SCHEME_OF_MATCH_ID
+};
struct hns3_mbx_resp_status {
rte_spinlock_t lock; /* protects against contending sync cmd resp */
+
+ uint8_t matching_scheme;
+
+ /* The following fields used in the matching scheme for original */
uint32_t req_msg_data;
uint32_t head;
uint32_t tail;
uint32_t lost;
+
+ /* The following fields used in the matching scheme for match_id */
+ uint16_t match_id;
+ bool received_match_resp;
+
int resp_status;
uint8_t additional_info[HNS3_MBX_MAX_RESP_DATA_SIZE];
};
uint8_t mbx_need_resp;
uint8_t rsv1;
uint8_t msg_len;
- uint8_t rsv2[3];
+ uint8_t rsv2;
+ uint16_t match_id;
uint8_t msg[HNS3_MBX_MAX_MSG_SIZE];
};
uint8_t dest_vfid;
uint8_t rsv[3];
uint8_t msg_len;
- uint8_t rsv1[3];
+ uint8_t rsv1;
+ uint16_t match_id;
uint16_t msg[8];
};
-struct hns3_vf_rst_cmd {
- uint8_t dest_vfid;
- uint8_t vf_rst;
- uint8_t rsv[22];
+struct hns3_ring_chain_param {
+ uint8_t ring_type;
+ uint8_t tqp_index;
+ uint8_t int_gl_index;
+};
+
+#define HNS3_MBX_MAX_RING_CHAIN_PARAM_NUM 4
+struct hns3_vf_bind_vector_msg {
+ uint8_t vector_id;
+ uint8_t ring_num;
+ struct hns3_ring_chain_param param[HNS3_MBX_MAX_RING_CHAIN_PARAM_NUM];
};
struct hns3_pf_rst_done_cmd {
#define HNS3_PF_RESET_DONE_BIT BIT(0)
-/* used by VF to store the received Async responses from PF */
-struct hns3_mbx_arq_ring {
-#define HNS3_MBX_MAX_ARQ_MSG_SIZE 8
-#define HNS3_MBX_MAX_ARQ_MSG_NUM 1024
- uint32_t head;
- uint32_t tail;
- uint32_t count;
- uint16_t msg_q[HNS3_MBX_MAX_ARQ_MSG_NUM][HNS3_MBX_MAX_ARQ_MSG_SIZE];
-};
-
#define hns3_mbx_ring_ptr_move_crq(crq) \
((crq)->next_to_use = ((crq)->next_to_use + 1) % (crq)->desc_num)
-#define hns3_mbx_tail_ptr_move_arq(arq) \
- ((arq).tail = ((arq).tail + 1) % HNS3_MBX_MAX_ARQ_MSG_SIZE)
-#define hns3_mbx_head_ptr_move_arq(arq) \
- ((arq).head = ((arq).head + 1) % HNS3_MBX_MAX_ARQ_MSG_SIZE)
struct hns3_hw;
void hns3_dev_handle_mbx_msg(struct hns3_hw *hw);