net/hns3: fix DCB configuration

[dpdk.git] / drivers / net / hns3 / hns3_regs.h

diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h
index 2f5faaf..5812eb3 100644 (file)
--- a/drivers/net/hns3/hns3_regs.h
+++ b/drivers/net/hns3/hns3_regs.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
  */
 
 #ifndef _HNS3_REGS_H_
@@ -27,6 +27,9 @@
 
 #define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800
 
+#define HNS3_RAS_PF_OTHER_INT_STS_REG  0x20B00
+#define HNS3_RAS_REG_NFE_MASK          0xFF00
+
 #define HNS3_MISC_VECTOR_REG_BASE      0x20400
 #define HNS3_VECTOR0_OTER_EN_REG       0x20600
 #define HNS3_MISC_RESET_STS_REG                0x20700
@@ -34,6 +37,9 @@
 #define HNS3_FUN_RST_ING               0x20C00
 #define HNS3_GRO_EN_REG                        0x28000
 
+#define HNS3_RPU_DROP_CNT_REG          0x28004
+#define HNS3_RXD_ADV_LAYOUT_EN_REG     0x28008
+
 /* Vector0 register bits for reset */
 #define HNS3_VECTOR0_FUNCRESET_INT_B   0
 #define HNS3_VECTOR0_GLOBALRESET_INT_B 5
@@ -80,20 +86,68 @@
 #define HNS3_RING_TX_BD_ERR_REG                        0x00074
 
 #define HNS3_RING_EN_REG                       0x00090
+#define HNS3_RING_RX_EN_REG                    0x00098
+#define HNS3_RING_TX_EN_REG                    0x000d4
 
 #define HNS3_RING_EN_B                         0
 
 #define HNS3_TQP_REG_OFFSET                    0x80000
 #define HNS3_TQP_REG_SIZE                      0x200
 
-/* bar registers for tqp interrupt */
-#define HNS3_TQP_INTR_CTRL_REG                 0x20000
-#define HNS3_TQP_INTR_GL0_REG                  0x20100
-#define HNS3_TQP_INTR_GL1_REG                  0x20200
-#define HNS3_TQP_INTR_GL2_REG                  0x20300
-#define HNS3_TQP_INTR_RL_REG                   0x20900
+#define HNS3_TQP_EXT_REG_OFFSET                        0x100
+#define HNS3_MIN_EXTEND_QUEUE_ID               1024
 
-#define HNS3_TQP_INTR_REG_SIZE                 4
+/* bar registers for tqp interrupt */
+#define HNS3_TQP_INTR_REG_BASE                 0x20000
+#define HNS3_TQP_INTR_EXT_REG_BASE             0x30000
+#define HNS3_TQP_INTR_CTRL_REG                 0
+#define HNS3_TQP_INTR_GL0_REG                  0x100
+#define HNS3_TQP_INTR_GL1_REG                  0x200
+#define HNS3_TQP_INTR_GL2_REG                  0x300
+#define HNS3_TQP_INTR_RL_REG                   0x900
+#define HNS3_TQP_INTR_TX_QL_REG                        0xe00
+#define HNS3_TQP_INTR_RX_QL_REG                        0xf00
+#define HNS3_TQP_INTR_RL_EN_B                  6
+
+#define HNS3_MIN_EXT_TQP_INTR_ID               64
+#define HNS3_TQP_INTR_LOW_ORDER_OFFSET         0x4
+#define HNS3_TQP_INTR_HIGH_ORDER_OFFSET                0x1000
+
+#define HNS3_TQP_INTR_GL_MAX                   0x1FE0
+#define HNS3_TQP_INTR_GL_DEFAULT               20
+#define HNS3_TQP_INTR_GL_UNIT_1US              BIT(31)
+#define HNS3_TQP_INTR_RL_MAX                   0xEC
+#define HNS3_TQP_INTR_RL_ENABLE_MASK           0x40
+#define HNS3_TQP_INTR_RL_DEFAULT               0
+#define HNS3_TQP_INTR_QL_DEFAULT               0
+
+/* Register bit for 1588 event */
+#define HNS3_VECTOR0_1588_INT_B                        0
+
+#define HNS3_PTP_BASE_ADDRESS                  0x29000
+
+#define HNS3_TX_1588_SEQID_BACK                        (HNS3_PTP_BASE_ADDRESS + 0x0)
+#define HNS3_TX_1588_TSP_BACK_0                        (HNS3_PTP_BASE_ADDRESS + 0x4)
+#define HNS3_TX_1588_TSP_BACK_1                        (HNS3_PTP_BASE_ADDRESS + 0x8)
+#define HNS3_TX_1588_TSP_BACK_2                        (HNS3_PTP_BASE_ADDRESS + 0xc)
+
+#define HNS3_TX_1588_BACK_TSP_CNT              (HNS3_PTP_BASE_ADDRESS + 0x30)
+
+#define HNS3_CFG_TIME_SYNC_H                   (HNS3_PTP_BASE_ADDRESS + 0x50)
+#define HNS3_CFG_TIME_SYNC_M                   (HNS3_PTP_BASE_ADDRESS + 0x54)
+#define HNS3_CFG_TIME_SYNC_L                   (HNS3_PTP_BASE_ADDRESS + 0x58)
+#define HNS3_CFG_TIME_SYNC_RDY                 (HNS3_PTP_BASE_ADDRESS + 0x5c)
+
+#define HNS3_CFG_TIME_CYC_EN                   (HNS3_PTP_BASE_ADDRESS + 0x70)
+
+#define HNS3_CURR_TIME_OUT_H                   (HNS3_PTP_BASE_ADDRESS + 0x74)
+#define HNS3_CURR_TIME_OUT_L                   (HNS3_PTP_BASE_ADDRESS + 0x78)
+#define HNS3_CURR_TIME_OUT_NS                  (HNS3_PTP_BASE_ADDRESS + 0x7c)
+
+/* gl_usec convert to hardware count, as writing each 1 represents 2us */
+#define HNS3_GL_USEC_TO_REG(gl_usec)           ((gl_usec) >> 1)
+/* rl_usec convert to hardware count, as writing each 1 represents 4us */
+#define HNS3_RL_USEC_TO_REG(rl_usec)           ((rl_usec) >> 2)
 
 int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs);
 #endif /* _HNS3_REGS_H_ */