net/enic: enable flow API for VF representor

[dpdk.git] / drivers / net / hns3 / hns3_regs.h

diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h
index 64bd693..5cf924e 100644 (file)
--- a/drivers/net/hns3/hns3_regs.h
+++ b/drivers/net/hns3/hns3_regs.h
@@ -27,6 +27,9 @@
 
 #define HNS3_VECTOR0_OTHER_INT_STS_REG 0x20800
 
+#define HNS3_RAS_PF_OTHER_INT_STS_REG  0x20B00
+#define HNS3_RAS_REG_NFE_MASK          0xFF00
+
 #define HNS3_MISC_VECTOR_REG_BASE      0x20400
 #define HNS3_VECTOR0_OTER_EN_REG       0x20600
 #define HNS3_MISC_RESET_STS_REG                0x20700
@@ -92,13 +95,17 @@
 #define HNS3_TQP_INTR_GL1_REG                  0x20200
 #define HNS3_TQP_INTR_GL2_REG                  0x20300
 #define HNS3_TQP_INTR_RL_REG                   0x20900
+#define HNS3_TQP_INTR_TX_QL_REG                        0x20e00
+#define HNS3_TQP_INTR_RX_QL_REG                        0x20f00
 
 #define HNS3_TQP_INTR_REG_SIZE                 4
 #define HNS3_TQP_INTR_GL_MAX                   0x1FE0
 #define HNS3_TQP_INTR_GL_DEFAULT               20
+#define HNS3_TQP_INTR_GL_UNIT_1US              BIT(31)
 #define HNS3_TQP_INTR_RL_MAX                   0xEC
 #define HNS3_TQP_INTR_RL_ENABLE_MASK           0x40
 #define HNS3_TQP_INTR_RL_DEFAULT               0
+#define HNS3_TQP_INTR_QL_DEFAULT               0
 
 /* gl_usec convert to hardware count, as writing each 1 represents 2us */
 #define HNS3_GL_USEC_TO_REG(gl_usec)           ((gl_usec) >> 1)