hns3_rx_queue_release_mbufs(rxq);
if (rxq->mz)
rte_memzone_free(rxq->mz);
- if (rxq->sw_ring)
- rte_free(rxq->sw_ring);
+ rte_free(rxq->sw_ring);
rte_free(rxq);
}
}
hns3_tx_queue_release_mbufs(txq);
if (txq->mz)
rte_memzone_free(txq->mz);
- if (txq->sw_ring)
- rte_free(txq->sw_ring);
- if (txq->free)
- rte_free(txq->free);
+ rte_free(txq->sw_ring);
+ rte_free(txq->free);
rte_free(txq);
}
}
rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
rxq->rx_ring_phys_addr = rx_mz->iova;
- hns3_dbg(hw, "No.%u rx descriptors iova 0x%" PRIx64, q_info->idx,
- rxq->rx_ring_phys_addr);
-
return rxq;
}
txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
txq->tx_ring_phys_addr = tx_mz->iova;
- hns3_dbg(hw, "No.%u tx descriptors iova 0x%" PRIx64, q_info->idx,
- txq->tx_ring_phys_addr);
-
/* Clear tx bd */
desc = txq->tx_ring;
for (i = 0; i < txq->nb_tx_desc; i++) {
* For hns3 VF device, whether it needs to process PVID depends
* on the configuration of PF kernel mode netdevice driver. And the
* related PF configuration is delivered through the mailbox and finally
- * reflectd in port_base_vlan_cfg.
+ * reflected in port_base_vlan_cfg.
*/
if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state ==
return rte_mbuf_raw_alloc(rxq->mb_pool);
}
-static inline void
+static void
hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf,
- volatile struct hns3_desc *rxd)
+ uint64_t timestamp)
{
struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns);
- uint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp);
- mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | RTE_MBUF_F_RX_IEEE1588_TMST;
+ mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP |
+ RTE_MBUF_F_RX_IEEE1588_TMST;
if (hns3_timestamp_rx_dynflag > 0) {
*RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = timestamp;
rxe->mbuf = nmb;
if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
- hns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp);
+ hns3_rx_ptp_timestamp_handle(rxq, rxm,
+ rte_le_to_cpu_64(rxdp->timestamp));
dma_addr = rte_mbuf_data_iova_default(nmb);
rxdp->addr = rte_cpu_to_le_64(dma_addr);
struct rte_mbuf *rxm;
struct rte_eth_dev *dev;
uint32_t bd_base_info;
+ uint64_t timestamp;
uint32_t l234_info;
uint32_t gro_size;
uint32_t ol_info;
rxm = rxe->mbuf;
rxe->mbuf = nmb;
+ if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
+ timestamp = rte_le_to_cpu_64(rxdp->timestamp);
+
dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
rxdp->rx.bd_base_info = 0;
rxdp->addr = dma_addr;
}
if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))
- hns3_rx_ptp_timestamp_handle(rxq, first_seg, rxdp);
+ hns3_rx_ptp_timestamp_handle(rxq, first_seg, timestamp);
/*
* The last buffer of the received packet. packet len from
* For hns3 VF device, whether it needs to process PVID depends
* on the configuration of PF kernel mode netdev driver. And the
* related PF configuration is delivered through the mailbox and finally
- * reflectd in port_base_vlan_cfg.
+ * reflected in port_base_vlan_cfg.
*/
if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
txq->pvid_sw_shift_en = hw->port_base_vlan_cfg.state ==
* in Tx direction based on hns3 network engine. So when the number of
* VLANs in the packets represented by rxm plus the number of VLAN
* offload by hardware such as PVID etc, exceeds two, the packets will
- * be discarded or the original VLAN of the packets will be overwitted
+ * be discarded or the original VLAN of the packets will be overwritten
* by hardware. When the PF PVID is enabled by calling the API function
* named rte_eth_dev_set_vlan_pvid or the VF PVID is enabled by the hns3
* PF kernel ether driver, the outer VLAN tag will always be the PVID.
/*
* The inner l2 length of mbuf is the sum of outer l4 length,
* tunneling header length and inner l2 length for a tunnel
- * packect. But in hns3 tx descriptor, the tunneling header
+ * packet. But in hns3 tx descriptor, the tunneling header
* length is contained in the field of outer L4 length.
* Therefore, driver need to calculate the outer L4 length and
* inner L2 length.
tmp_outer |= hns3_gen_field_val(HNS3_TXD_TUNTYPE_M,
HNS3_TXD_TUNTYPE_S, HNS3_TUN_NVGRE);
/*
- * For NVGRE tunnel packect, the outer L4 is empty. So only
+ * For NVGRE tunnel packet, the outer L4 is empty. So only
* fill the NVGRE header length to the outer L4 field.
*/
tmp_outer |= hns3_gen_field_val(HNS3_TXD_L4LEN_M,
* mbuf, but for hns3 descriptor, it is contained in the outer L4. So,
* there is a need that switching between them. To avoid multiple
* calculations, the length of the L2 header include the outer and
- * inner, will be filled during the parsing of tunnel packects.
+ * inner, will be filled during the parsing of tunnel packets.
*/
if (!(ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)) {
/*
if (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM) {
struct rte_udp_hdr *udp_hdr;
/*
- * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo
+ * If OUTER_UDP_CKSUM is support, HW can calculate the pseudo
* header for TSO packets
*/
if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
if (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM) {
struct rte_udp_hdr *udp_hdr;
/*
- * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo
+ * If OUTER_UDP_CKSUM is support, HW can calculate the pseudo
* header for TSO packets
*/
if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
{
#define PER_LOOP_NUM 4
- const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
+ uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
uint64_t dma_addr;
uint32_t i;
txdp->tx.paylen_fd_dop_ol4cs = 0;
txdp->tx.type_cs_vlan_tso_len = 0;
txdp->tx.ol_type_vlan_len_msec = 0;
+ if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST))
+ bd_flag |= BIT(HNS3_TXD_TSYN_B);
txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
}
}
static inline void
hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts)
{
- const uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
+ uint16_t bd_flag = BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B);
uint64_t dma_addr;
dma_addr = rte_mbuf_data_iova(*pkts);
txdp->tx.paylen_fd_dop_ol4cs = 0;
txdp->tx.type_cs_vlan_tso_len = 0;
txdp->tx.ol_type_vlan_len_msec = 0;
+ if (unlikely((*pkts)->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST))
+ bd_flag |= BIT(HNS3_TXD_TSYN_B);
txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag);
}
{
uint64_t offloads = dev->data->dev_conf.txmode.offloads;
- struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- if (hns3_dev_get_support(hw, PTP))
- return false;
-
return (offloads == (offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE));
}
return hns3_xmit_pkts;
}
-uint16_t
-hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
- struct rte_mbuf **pkts __rte_unused,
- uint16_t pkts_n __rte_unused)
-{
- return 0;
-}
-
static void
hns3_trace_rxtx_function(struct rte_eth_dev *dev)
{
rx_mode.info, tx_mode.info);
}
-void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
+static void
+hns3_eth_dev_fp_ops_config(const struct rte_eth_dev *dev)
+{
+ struct rte_eth_fp_ops *fpo = rte_eth_fp_ops;
+ uint16_t port_id = dev->data->port_id;
+
+ fpo[port_id].rx_pkt_burst = dev->rx_pkt_burst;
+ fpo[port_id].tx_pkt_burst = dev->tx_pkt_burst;
+ fpo[port_id].tx_pkt_prepare = dev->tx_pkt_prepare;
+ fpo[port_id].rx_descriptor_status = dev->rx_descriptor_status;
+ fpo[port_id].tx_descriptor_status = dev->tx_descriptor_status;
+}
+
+void
+hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
struct hns3_adapter *hns = eth_dev->data->dev_private;
eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status;
eth_dev->tx_pkt_burst = hw->set_link_down ?
- hns3_dummy_rxtx_burst :
+ rte_eth_pkt_burst_dummy :
hns3_get_tx_function(eth_dev, &prep);
eth_dev->tx_pkt_prepare = prep;
eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status;
hns3_trace_rxtx_function(eth_dev);
} else {
- eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
- eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
+ eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
+ eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
eth_dev->tx_pkt_prepare = NULL;
}
+
+ hns3_eth_dev_fp_ops_config(eth_dev);
}
void
if (dev->tx_pkt_burst == hns3_xmit_pkts)
return hns3_tx_done_cleanup_full(q, free_cnt);
- else if (dev->tx_pkt_burst == hns3_dummy_rxtx_burst)
+ else if (dev->tx_pkt_burst == rte_eth_pkt_burst_dummy)
return 0;
else
return -ENOTSUP;
void
hns3_stop_tx_datapath(struct rte_eth_dev *dev)
{
- dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
+ dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
dev->tx_pkt_prepare = NULL;
+ hns3_eth_dev_fp_ops_config(dev);
+
+ if (rte_eal_process_type() == RTE_PROC_SECONDARY)
+ return;
+
rte_wmb();
/* Disable tx datapath on secondary process. */
hns3_mp_req_stop_tx(dev);
dev->tx_pkt_burst = hns3_get_tx_function(dev, &prep);
dev->tx_pkt_prepare = prep;
+ hns3_eth_dev_fp_ops_config(dev);
+
+ if (rte_eal_process_type() == RTE_PROC_SECONDARY)
+ return;
+
hns3_mp_req_start_tx(dev);
}
git.droids-corp.org / dpdk.git / blobdiff