#define HNS3_ALIGN_RING_DESC 32
#define HNS3_RING_BASE_ALIGN 128
+#define HNS3_512_BD_BUF_SIZE 512
+#define HNS3_1K_BD_BUF_SIZE 1024
+#define HNS3_2K_BD_BUF_SIZE 2048
+#define HNS3_4K_BD_BUF_SIZE 4096
+
+#define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE
+#define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE
+
#define HNS3_BD_SIZE_512_TYPE 0
#define HNS3_BD_SIZE_1024_TYPE 1
#define HNS3_BD_SIZE_2048_TYPE 2
uint16_t rx_buf_len;
uint16_t rx_free_thresh;
+ /*
+ * port based vlan configuration state.
+ * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
+ */
+ uint16_t pvid_state;
+
+ /* 4 if DEV_RX_OFFLOAD_KEEP_CRC offload set, 0 otherwise */
+ uint8_t crc_len;
+
bool rx_deferred_start; /* don't start this queue in dev start */
bool configured; /* indicate if rx queue has been configured */
uint16_t next_to_use;
uint16_t tx_bd_ready;
+ /*
+ * port based vlan configuration state.
+ * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
+ */
+ uint16_t pvid_state;
+
bool tx_deferred_start; /* don't start this queue in dev start */
bool configured; /* indicate if tx queue has been configured */
uint16_t nb_tx_q);
int hns3_config_gro(struct hns3_hw *hw, bool en);
int hns3_restore_gro_conf(struct hns3_hw *hw);
+void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);
#endif /* _HNS3_RXTX_H_ */