#define HNS3_BULK_ALLOC_MBUF_NUM 32
#define HNS3_DEFAULT_RX_FREE_THRESH 32
+#define HNS3_DEFAULT_TX_FREE_THRESH 32
+#define HNS3_DEFAULT_TX_RS_THRESH 32
+#define HNS3_TX_FAST_FREE_AHEAD 64
+
+#define HNS3_DEFAULT_RX_BURST 32
+#if (HNS3_DEFAULT_RX_BURST > 64)
+#error "PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\n"
+#endif
+#define HNS3_DEFAULT_DESCS_PER_LOOP 4
+#define HNS3_SVE_DEFAULT_DESCS_PER_LOOP 8
+#if (HNS3_DEFAULT_DESCS_PER_LOOP > HNS3_SVE_DEFAULT_DESCS_PER_LOOP)
+#define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_DEFAULT_DESCS_PER_LOOP
+#else
+#define HNS3_VECTOR_RX_OFFSET_TABLE_LEN HNS3_SVE_DEFAULT_DESCS_PER_LOOP
+#endif
+#define HNS3_DEFAULT_RXQ_REARM_THRESH 64
+#define HNS3_UINT8_BIT 8
+#define HNS3_UINT16_BIT 16
+#define HNS3_UINT32_BIT 32
#define HNS3_512_BD_BUF_SIZE 512
#define HNS3_1K_BD_BUF_SIZE 1024
#define HNS3_L3_LEN_UNIT 2UL
#define HNS3_L4_LEN_UNIT 2UL
+#define HNS3_TXD_DEFAULT_BDTYPE 0
+#define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
+#define HNS3_TXD_FE_CMD (0x1 << HNS3_TXD_FE_B)
+#define HNS3_TXD_DEFAULT_VLD_FE_BDTYPE \
+ (HNS3_TXD_VLD_CMD | HNS3_TXD_FE_CMD | HNS3_TXD_DEFAULT_BDTYPE)
+#define HNS3_TXD_SEND_SIZE_SHIFT 16
+
enum hns3_pkt_l2t_type {
HNS3_L2_TYPE_UNICAST,
HNS3_L2_TYPE_MULTICAST,
uint16_t ot_vlan_tag;
};
};
- uint32_t bd_base_info;
+ union {
+ uint32_t bd_base_info;
+ struct {
+ uint16_t bdtype_vld_udp0;
+ uint16_t fe_lum_crcp_l3l4p;
+ };
+ };
} rx;
};
} __rte_packed;
uint16_t rx_free_thresh;
uint16_t next_to_use; /* index of next BD to be polled */
uint16_t rx_free_hold; /* num of BDs waited to passed to hardware */
-
+ uint16_t rx_rearm_start; /* index of BD that driver re-arming from */
+ uint16_t rx_rearm_nb; /* number of remaining BDs to be re-armed */
/*
* port based vlan configuration state.
* value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
struct rte_mbuf *bulk_mbuf[HNS3_BULK_ALLOC_MBUF_NUM];
uint16_t bulk_mbuf_num;
+
+ /* offset_table: used for vector, to solve execute re-order problem */
+ uint8_t offset_table[HNS3_VECTOR_RX_OFFSET_TABLE_LEN + 1];
+ uint64_t mbuf_initializer; /* value to init mbufs used with vector rx */
+ struct rte_mbuf fake_mbuf; /* fake mbuf used with vector rx */
};
struct hns3_tx_queue {
void *io_base;
+ volatile void *io_tail_reg;
struct hns3_adapter *hns;
struct hns3_desc *tx_ring;
uint64_t tx_ring_phys_addr; /* TX ring DMA address */
uint16_t queue_id;
uint16_t port_id;
uint16_t nb_tx_desc;
+ /*
+ * index of next BD whose corresponding rte_mbuf can be released by
+ * driver.
+ */
uint16_t next_to_clean;
+ /* index of next BD to be filled by driver to send packet */
uint16_t next_to_use;
+ /* num of remaining BDs ready to be filled by driver to send packet */
uint16_t tx_bd_ready;
+ /* threshold for free tx buffer if available BDs less than this value */
+ uint16_t tx_free_thresh;
+
+ /*
+ * For better performance in tx datapath, releasing mbuf in batches is
+ * required.
+ * Only checking the VLD bit of the last descriptor in a batch of the
+ * thresh descriptors does not mean that these descriptors are all sent
+ * by hardware successfully. So we need to check that the VLD bits of
+ * all descriptors are cleared. and then free all mbufs in the batch.
+ * - tx_rs_thresh
+ * Number of mbufs released at a time.
+ *
+ * - free
+ * Tx mbuf free array used for preserving temporarily address of mbuf
+ * released back to mempool, when releasing mbuf in batches.
+ */
+ uint16_t tx_rs_thresh;
+ struct rte_mbuf **free;
+
/*
* port based vlan configuration state.
* value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE
uint64_t pkt_padding_fail_cnt;
};
+#define HNS3_GET_TX_QUEUE_PEND_BD_NUM(txq) \
+ ((txq)->nb_tx_desc - 1 - (txq)->tx_bd_ready)
+
struct hns3_queue_info {
const char *type; /* point to queue memory name */
const char *ring_name; /* point to hardware ring name */
void hns3_enable_all_queues(struct hns3_hw *hw, bool en);
int hns3_start_queues(struct hns3_adapter *hns, bool reset_queue);
int hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue);
+int hns3_rxq_iterate(struct rte_eth_dev *dev,
+ int (*callback)(struct hns3_rx_queue *, void *), void *arg);
void hns3_dev_release_mbufs(struct hns3_adapter *hns);
int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
unsigned int socket, const struct rte_eth_rxconf *conf,
uint16_t nb_pkts);
uint16_t hns3_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
+uint16_t hns3_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
int hns3_rx_burst_mode_get(struct rte_eth_dev *dev,
__rte_unused uint16_t queue_id,
struct rte_eth_burst_mode *mode);
+int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,
+ __rte_unused uint16_t queue_id,
+ struct rte_eth_burst_mode *mode);
const uint32_t *hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
void hns3_init_rx_ptype_tble(struct rte_eth_dev *dev);
void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev);
void hns3_update_all_queues_pvid_state(struct hns3_hw *hw);
void hns3_rx_scattered_reset(struct rte_eth_dev *dev);
void hns3_rx_scattered_calc(struct rte_eth_dev *dev);
+int hns3_rx_check_vec_support(struct rte_eth_dev *dev);
+int hns3_tx_check_vec_support(struct rte_eth_dev *dev);
+void hns3_rxq_vec_setup(struct hns3_rx_queue *rxq);
void hns3_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
struct rte_eth_rxq_info *qinfo);
void hns3_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,