#define HNS3_TXD_MSS_S 0
#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
+#define HNS3_TXD_OL4CS_B 22
#define HNS3_L2_LEN_UNIT 1UL
#define HNS3_L3_LEN_UNIT 2UL
#define HNS3_L4_LEN_UNIT 2UL
};
};
- uint32_t paylen;
+ uint32_t paylen_fd_dop_ol4cs;
uint16_t tp_fe_sc_vld_ra_ri;
uint16_t mss;
} tx;
};
#define HNS3_TX_CKSUM_OFFLOAD_MASK ( \
+ PKT_TX_OUTER_UDP_CKSUM | \
PKT_TX_OUTER_IP_CKSUM | \
PKT_TX_IP_CKSUM | \
PKT_TX_TCP_SEG | \
void hns3_restore_tqp_enable_state(struct hns3_hw *hw);
int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt);
void hns3_enable_rxd_adv_layout(struct hns3_hw *hw);
+int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
+int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
#endif /* _HNS3_RXTX_H_ */