/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2020 Hisilicon Limited.
+ * Copyright(c) 2020-2021 HiSilicon Limited.
*/
#include <arm_sve.h>
#include <rte_io.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include "hns3_ethdev.h"
#include "hns3_rxtx.h"
uint32_t bd_vld_num)
{
uint32_t retcode = 0;
- uint32_t cksum_err;
int ret, i;
for (i = 0; i < (int)bd_vld_num; i++) {
rx_pkts[i]->ol_flags = PKT_RX_RSS_HASH;
ret = hns3_handle_bdinfo(rxq, rx_pkts[i], key->bd_base_info[i],
- key->l234_info[i], &cksum_err);
+ key->l234_info[i]);
if (unlikely(ret)) {
retcode |= 1u << i;
continue;
rx_pkts[i]->packet_type = hns3_rx_calc_ptype(rxq,
key->l234_info[i], key->ol_info[i]);
- if (likely(key->bd_base_info[i] & BIT(HNS3_RXD_L3L4P_B)))
- hns3_rx_set_cksum_flag(rx_pkts[i],
- rx_pkts[i]->packet_type, cksum_err);
+
+ /* Increment bytes counter */
+ rxq->basic_stats.bytes += rx_pkts[i]->pkt_len;
}
return retcode;
svuint32_t rss_tbl1 = svld1_u32(PG32_256BIT, rss_adjust);
svuint32_t rss_tbl2 = svld1_u32(PG32_256BIT, &rss_adjust[8]);
+ /* compile-time verifies the xlen_adjust mask */
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
+ offsetof(struct rte_mbuf, pkt_len) + 4);
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
+ offsetof(struct rte_mbuf, data_len) + 2);
+
for (pos = 0; pos < nb_pkts; pos += HNS3_SVE_DEFAULT_DESCS_PER_LOOP,
rxdp += HNS3_SVE_DEFAULT_DESCS_PER_LOOP) {
svuint64_t vld_clz, mbp1st, mbp2st, mbuf_init;
{
struct hns3_rx_queue *rxq = rx_queue;
struct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use];
- uint64_t bd_err_mask; /* bit mask indicate whick pkts is error */
+ uint64_t pkt_err_mask; /* bit mask indicate whick pkts is error */
uint16_t nb_rx;
rte_prefetch_non_temporal(rxdp);
- nb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);
nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)
hns3_rx_prefetch_mbuf_sve(&rxq->sw_ring[rxq->next_to_use]);
- bd_err_mask = 0;
- nb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts, &bd_err_mask);
- if (unlikely(bd_err_mask))
- nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask);
+ if (likely(nb_pkts <= HNS3_DEFAULT_RX_BURST)) {
+ pkt_err_mask = 0;
+ nb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts,
+ &pkt_err_mask);
+ nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, pkt_err_mask);
+ return nb_rx;
+ }
+
+ nb_rx = 0;
+ while (nb_pkts > 0) {
+ uint16_t ret, n;
+
+ n = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);
+ pkt_err_mask = 0;
+ ret = hns3_recv_burst_vec_sve(rxq, &rx_pkts[nb_rx], n,
+ &pkt_err_mask);
+ nb_pkts -= ret;
+ nb_rx += hns3_rx_reassemble_pkts(&rx_pkts[nb_rx], ret,
+ pkt_err_mask);
+ if (ret < n)
+ break;
+
+ if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)
+ hns3_rxq_rearm_mbuf_sve(rxq);
+ }
return nb_rx;
}
(uint64_t *)&txdp->tx.outer_vlan_tag,
offsets, svdup_n_u64(0));
/* save offset 24~31byte of every BD */
- svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen,
- offsets, svdup_n_u64(valid_bit));
+ svst1_scatter_u64offset_u64(pg,
+ (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs,
+ offsets, svdup_n_u64(valid_bit));
+
+ /* Increment bytes counter */
+ uint32_t idx;
+ for (idx = 0; idx < svcntd(); idx++)
+ txq->basic_stats.bytes += pkts[idx]->pkt_len;
/* update index for next loop */
i += svcntd();
nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
if (unlikely(nb_pkts == 0)) {
- txq->queue_full_cnt++;
+ txq->dfx_stats.queue_full_cnt++;
return 0;
}