#include "hns3_logs.h"
#include "hns3_regs.h"
+/* The statistics of the per-rxq basic stats */
+static const struct hns3_xstats_name_offset hns3_rxq_basic_stats_strings[] = {
+ {"packets",
+ HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(packets)},
+ {"bytes",
+ HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(bytes)},
+ {"errors",
+ HNS3_RXQ_BASIC_STATS_FIELD_OFFSET(errors)}
+};
+
+/* The statistics of the per-txq basic stats */
+static const struct hns3_xstats_name_offset hns3_txq_basic_stats_strings[] = {
+ {"packets",
+ HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(packets)},
+ {"bytes",
+ HNS3_TXQ_BASIC_STATS_FIELD_OFFSET(bytes)}
+};
+
/* MAC statistics */
static const struct hns3_xstats_name_offset hns3_mac_strings[] = {
{"mac_tx_mac_pause_num",
{"TX_QUEUE_FBD", HNS3_RING_TX_FBDNUM_REG}
};
+/* The statistic of imissed packet */
+static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = {
+ {"RPU_DROP_CNT",
+ HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)},
+};
+
#define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \
sizeof(hns3_mac_strings[0]))
#define HNS3_NUM_TX_QUEUE_STATS (sizeof(hns3_tx_queue_strings) / \
sizeof(hns3_tx_queue_strings[0]))
+#define HNS3_NUM_RXQ_BASIC_STATS (sizeof(hns3_rxq_basic_stats_strings) / \
+ sizeof(hns3_rxq_basic_stats_strings[0]))
+
+#define HNS3_NUM_TXQ_BASIC_STATS (sizeof(hns3_txq_basic_stats_strings) / \
+ sizeof(hns3_txq_basic_stats_strings[0]))
+
+#define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \
+ sizeof(hns3_imissed_stats_strings[0]))
+
#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \
- HNS3_NUM_RESET_XSTATS)
+ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS)
static void hns3_tqp_stats_clear(struct hns3_hw *hw);
return ret;
}
-/* Get tqp stats from register */
static int
-hns3_update_tqp_stats(struct hns3_hw *hw)
+hns3_update_rpu_drop_stats(struct hns3_hw *hw)
{
- struct hns3_tqp_stats *stats = &hw->tqp_stats;
+ struct hns3_rx_missed_stats *stats = &hw->imissed_stats;
+ struct hns3_query_rpu_cmd *req;
struct hns3_cmd_desc desc;
uint64_t cnt;
- uint16_t i;
+ uint32_t tc_num;
int ret;
- for (i = 0; i < hw->tqps_num; i++) {
- hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_RX_STATUS,
- true);
+ hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_DFX_RPU_REG_0, true);
+ req = (struct hns3_query_rpu_cmd *)desc.data;
- desc.data[0] = rte_cpu_to_le_32((uint32_t)i);
- ret = hns3_cmd_send(hw, &desc, 1);
- if (ret) {
- hns3_err(hw, "Failed to query RX No.%u queue stat: %d",
- i, ret);
- return ret;
- }
- cnt = rte_le_to_cpu_32(desc.data[1]);
- stats->rcb_rx_ring_pktnum_rcd += cnt;
- stats->rcb_rx_ring_pktnum[i] += cnt;
+ /*
+ * tc_num is 0, means rpu stats of all TC channels will be
+ * get from firmware
+ */
+ tc_num = 0;
+ req->tc_queue_num = rte_cpu_to_le_32(tc_num);
+ ret = hns3_cmd_send(hw, &desc, 1);
+ if (ret) {
+ hns3_err(hw, "failed to query RPU stats: %d", ret);
+ return ret;
+ }
- hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_TX_STATUS,
- true);
+ cnt = rte_le_to_cpu_32(req->rpu_rx_pkt_drop_cnt);
+ stats->rpu_rx_drop_cnt += cnt;
- desc.data[0] = rte_cpu_to_le_32((uint32_t)i);
- ret = hns3_cmd_send(hw, &desc, 1);
- if (ret) {
- hns3_err(hw, "Failed to query TX No.%u queue stat: %d",
- i, ret);
- return ret;
- }
- cnt = rte_le_to_cpu_32(desc.data[1]);
- stats->rcb_tx_ring_pktnum_rcd += cnt;
- stats->rcb_tx_ring_pktnum[i] += cnt;
- }
+ return 0;
+}
+
+int
+hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear)
+{
+ int ret;
+
+ ret = hns3_update_rpu_drop_stats(hw);
+ if (ret)
+ return ret;
+
+ if (is_clear)
+ memset(&hw->imissed_stats, 0, sizeof(hw->imissed_stats));
return 0;
}
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
+ struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
struct hns3_tqp_stats *stats = &hw->tqp_stats;
struct hns3_rx_queue *rxq;
struct hns3_tx_queue *txq;
uint64_t cnt;
- uint64_t num;
uint16_t i;
int ret;
- /* Update tqp stats by read register */
- ret = hns3_update_tqp_stats(hw);
- if (ret) {
- hns3_err(hw, "Update tqp stats fail : %d", ret);
- return ret;
+ if (!hns->is_vf) {
+ /* Update imissed stats */
+ ret = hns3_update_imissed_stats(hw, false);
+ if (ret) {
+ hns3_err(hw, "update imissed stats failed, ret = %d",
+ ret);
+ return ret;
+ }
+
+ rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt;
}
- /* Get the error stats of received packets */
- num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, eth_dev->data->nb_rx_queues);
- for (i = 0; i != num; ++i) {
+ /* Reads all the stats of a rxq in a loop to keep them synchronized */
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
rxq = eth_dev->data->rx_queues[i];
- if (rxq) {
- cnt = rxq->err_stats.l2_errors +
- rxq->err_stats.pkt_len_errors;
- rte_stats->q_errors[i] = cnt;
- rte_stats->q_ipackets[i] =
- stats->rcb_rx_ring_pktnum[i] - cnt;
- rte_stats->ierrors += cnt;
- }
+ if (rxq == NULL)
+ continue;
+
+ cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
+ /*
+ * Read hardware and software in adjacent positions to minumize
+ * the timing variance.
+ */
+ rte_stats->ierrors += rxq->err_stats.l2_errors +
+ rxq->err_stats.pkt_len_errors;
+ stats->rcb_rx_ring_pktnum_rcd += cnt;
+ stats->rcb_rx_ring_pktnum[i] += cnt;
+ rte_stats->ibytes += rxq->basic_stats.bytes;
}
- /* Get the error stats of transmitted packets */
- num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, eth_dev->data->nb_tx_queues);
- for (i = 0; i < num; i++) {
+
+ /* Reads all the stats of a txq in a loop to keep them synchronized */
+ for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
txq = eth_dev->data->tx_queues[i];
- if (txq)
- rte_stats->q_opackets[i] = stats->rcb_tx_ring_pktnum[i];
+ if (txq == NULL)
+ continue;
+
+ cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
+ stats->rcb_tx_ring_pktnum_rcd += cnt;
+ stats->rcb_tx_ring_pktnum[i] += cnt;
+ rte_stats->obytes += txq->basic_stats.bytes;
}
rte_stats->oerrors = 0;
- rte_stats->ipackets = stats->rcb_rx_ring_pktnum_rcd -
- rte_stats->ierrors;
+ /*
+ * If HW statistics are reset by stats_reset, but a lot of residual
+ * packets exist in the hardware queue and these packets are error
+ * packets, flip overflow may occurred. So return 0 in this case.
+ */
+ rte_stats->ipackets =
+ stats->rcb_rx_ring_pktnum_rcd > rte_stats->ierrors ?
+ stats->rcb_rx_ring_pktnum_rcd - rte_stats->ierrors : 0;
rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd -
rte_stats->oerrors;
rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed;
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- struct hns3_cmd_desc desc_reset;
struct hns3_rx_queue *rxq;
+ struct hns3_tx_queue *txq;
uint16_t i;
int ret;
- /*
- * Note: Reading hardware statistics of rx/tx queue packet number
- * will clear them.
- */
- for (i = 0; i < hw->tqps_num; i++) {
- hns3_cmd_setup_basic_desc(&desc_reset, HNS3_OPC_QUERY_RX_STATUS,
- true);
- desc_reset.data[0] = rte_cpu_to_le_32((uint32_t)i);
- ret = hns3_cmd_send(hw, &desc_reset, 1);
+ if (!hns->is_vf) {
+ /*
+ * Note: Reading hardware statistics of imissed registers will
+ * clear them.
+ */
+ ret = hns3_update_imissed_stats(hw, true);
if (ret) {
- hns3_err(hw, "Failed to reset RX No.%u queue stat: %d",
- i, ret);
+ hns3_err(hw, "clear imissed stats failed, ret = %d",
+ ret);
return ret;
}
+ }
- hns3_cmd_setup_basic_desc(&desc_reset, HNS3_OPC_QUERY_TX_STATUS,
- true);
- desc_reset.data[0] = rte_cpu_to_le_32((uint32_t)i);
- ret = hns3_cmd_send(hw, &desc_reset, 1);
- if (ret) {
- hns3_err(hw, "Failed to reset TX No.%u queue stat: %d",
- i, ret);
- return ret;
- }
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ rxq = eth_dev->data->rx_queues[i];
+ if (rxq == NULL)
+ continue;
+
+ rxq->err_stats.pkt_len_errors = 0;
+ rxq->err_stats.l2_errors = 0;
}
- /*
- * Clear soft stats of rx error packet which will be dropped
- * in driver.
- */
+ /* Clear all the stats of a rxq in a loop to keep them synchronized */
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
rxq = eth_dev->data->rx_queues[i];
- if (rxq) {
- rxq->err_stats.pkt_len_errors = 0;
- rxq->err_stats.l2_errors = 0;
- }
+ if (rxq == NULL)
+ continue;
+
+ memset(&rxq->basic_stats, 0,
+ sizeof(struct hns3_rx_basic_stats));
+
+ /* This register is read-clear */
+ (void)hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
+ rxq->err_stats.pkt_len_errors = 0;
+ rxq->err_stats.l2_errors = 0;
+ }
+
+ /* Clear all the stats of a txq in a loop to keep them synchronized */
+ for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
+ txq = eth_dev->data->tx_queues[i];
+ if (txq == NULL)
+ continue;
+
+ memset(&txq->basic_stats, 0,
+ sizeof(struct hns3_tx_basic_stats));
+
+ /* This register is read-clear */
+ (void)hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
}
hns3_tqp_stats_clear(hw);
static int
hns3_xstats_calc_num(struct rte_eth_dev *dev)
{
+#define HNS3_PF_VF_RX_COMM_STATS_NUM (HNS3_NUM_RX_BD_ERROR_XSTATS + \
+ HNS3_NUM_RXQ_DFX_XSTATS + \
+ HNS3_NUM_RX_QUEUE_STATS + \
+ HNS3_NUM_RXQ_BASIC_STATS)
+#define HNS3_PF_VF_TX_COMM_STATS_NUM (HNS3_NUM_TXQ_DFX_XSTATS + \
+ HNS3_NUM_TX_QUEUE_STATS + \
+ HNS3_NUM_TXQ_BASIC_STATS)
+
struct hns3_adapter *hns = dev->data->dev_private;
uint16_t nb_rx_q = dev->data->nb_rx_queues;
uint16_t nb_tx_q = dev->data->nb_tx_queues;
- int bderr_stats = nb_rx_q * HNS3_NUM_RX_BD_ERROR_XSTATS;
- int rx_dfx_stats = nb_rx_q * HNS3_NUM_RXQ_DFX_XSTATS;
- int tx_dfx_stats = nb_tx_q * HNS3_NUM_TXQ_DFX_XSTATS;
- int rx_queue_stats = nb_rx_q * HNS3_NUM_RX_QUEUE_STATS;
- int tx_queue_stats = nb_tx_q * HNS3_NUM_TX_QUEUE_STATS;
+ int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM;
+ int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM;
if (hns->is_vf)
- return bderr_stats + rx_dfx_stats + tx_dfx_stats +
- rx_queue_stats + tx_queue_stats + HNS3_NUM_RESET_XSTATS;
+ return rx_comm_stats_num + tx_comm_stats_num +
+ HNS3_NUM_RESET_XSTATS;
else
- return bderr_stats + rx_dfx_stats + tx_dfx_stats +
- rx_queue_stats + tx_queue_stats + HNS3_FIX_NUM_STATS;
+ return rx_comm_stats_num + tx_comm_stats_num +
+ HNS3_FIX_NUM_STATS;
}
static void
hns3_rxq_dfx_stats_get(dev, xstats, count);
hns3_txq_dfx_stats_get(dev, xstats, count);
}
+
+static void
+hns3_rxq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
+ int *count)
+{
+ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct hns3_tqp_stats *stats = &hw->tqp_stats;
+ struct hns3_rx_basic_stats *rxq_stats;
+ struct hns3_rx_queue *rxq;
+ uint16_t i, j;
+ uint32_t cnt;
+ char *val;
+
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
+ rxq = dev->data->rx_queues[i];
+ if (rxq == NULL)
+ continue;
+
+ cnt = hns3_read_dev(rxq, HNS3_RING_RX_PKTNUM_RECORD_REG);
+ /*
+ * Read hardware and software in adjacent positions to minimize
+ * the time difference.
+ */
+ rxq_stats = &rxq->basic_stats;
+ rxq_stats->errors = rxq->err_stats.l2_errors +
+ rxq->err_stats.pkt_len_errors;
+ stats->rcb_rx_ring_pktnum_rcd += cnt;
+ stats->rcb_rx_ring_pktnum[i] += cnt;
+
+ /*
+ * If HW statistics are reset by stats_reset, but a lot of
+ * residual packets exist in the hardware queue and these
+ * packets are error packets, flip overflow may occurred.
+ * So return 0 in this case.
+ */
+ rxq_stats->packets =
+ stats->rcb_rx_ring_pktnum[i] > rxq_stats->errors ?
+ stats->rcb_rx_ring_pktnum[i] - rxq_stats->errors : 0;
+ for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
+ val = (char *)rxq_stats +
+ hns3_rxq_basic_stats_strings[j].offset;
+ xstats[*count].value = *(uint64_t *)val;
+ xstats[*count].id = *count;
+ (*count)++;
+ }
+ }
+}
+
+static void
+hns3_txq_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
+ int *count)
+{
+ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct hns3_tqp_stats *stats = &hw->tqp_stats;
+ struct hns3_tx_basic_stats *txq_stats;
+ struct hns3_tx_queue *txq;
+ uint16_t i, j;
+ uint32_t cnt;
+ char *val;
+
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ txq = dev->data->tx_queues[i];
+ if (txq == NULL)
+ continue;
+
+ cnt = hns3_read_dev(txq, HNS3_RING_TX_PKTNUM_RECORD_REG);
+ stats->rcb_tx_ring_pktnum_rcd += cnt;
+ stats->rcb_tx_ring_pktnum[i] += cnt;
+
+ txq_stats = &txq->basic_stats;
+ txq_stats->packets = stats->rcb_tx_ring_pktnum[i];
+
+ for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
+ val = (char *)txq_stats +
+ hns3_txq_basic_stats_strings[j].offset;
+ xstats[*count].value = *(uint64_t *)val;
+ xstats[*count].id = *count;
+ (*count)++;
+ }
+ }
+}
+
+static void
+hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
+ int *count)
+{
+ hns3_rxq_basic_stats_get(dev, xstats, count);
+ hns3_txq_basic_stats_get(dev, xstats, count);
+}
+
/*
* Retrieve extended(tqp | Mac) statistics of an Ethernet device.
* @param dev
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_pf *pf = &hns->pf;
struct hns3_hw *hw = &hns->hw;
+ struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats;
struct hns3_mac_stats *mac_stats = &hw->mac_stats;
struct hns3_reset_stats *reset_stats = &hw->reset.stats;
struct hns3_rx_bd_errors_stats *rx_err_stats;
count = 0;
+ hns3_tqp_basic_stats_get(dev, xstats, &count);
+
if (!hns->is_vf) {
/* Update Mac stats */
ret = hns3_query_update_mac_stats(dev);
count++;
}
+ ret = hns3_update_imissed_stats(hw, false);
+ if (ret) {
+ hns3_err(hw, "update imissed stats failed, ret = %d",
+ ret);
+ return ret;
+ }
+
+ for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) {
+ addr = (char *)imissed_stats +
+ hns3_imissed_stats_strings[i].offset;
+ xstats[count].value = *(uint64_t *)addr;
+ xstats[count].id = count;
+ count++;
+ }
+
for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
addr = (char *)&pf->abn_int_stats +
hns3_error_int_stats_strings[i].offset;
return count;
}
+static void
+hns3_tqp_basic_stats_name_get(struct rte_eth_dev *dev,
+ struct rte_eth_xstat_name *xstats_names,
+ uint32_t *count)
+{
+ uint16_t i, j;
+
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
+ for (j = 0; j < HNS3_NUM_RXQ_BASIC_STATS; j++) {
+ snprintf(xstats_names[*count].name,
+ sizeof(xstats_names[*count].name),
+ "rx_q%u_%s", i,
+ hns3_rxq_basic_stats_strings[j].name);
+ (*count)++;
+ }
+ }
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ for (j = 0; j < HNS3_NUM_TXQ_BASIC_STATS; j++) {
+ snprintf(xstats_names[*count].name,
+ sizeof(xstats_names[*count].name),
+ "tx_q%u_%s", i,
+ hns3_txq_basic_stats_strings[j].name);
+ (*count)++;
+ }
+ }
+}
+
static void
hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev,
struct rte_eth_xstat_name *xstats_names,
{
uint16_t i, j;
- for (j = 0; j < dev->data->nb_rx_queues; j++) {
- for (i = 0; i < HNS3_NUM_RXQ_DFX_XSTATS; i++) {
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
+ for (j = 0; j < HNS3_NUM_RXQ_DFX_XSTATS; j++) {
snprintf(xstats_names[*count].name,
sizeof(xstats_names[*count].name),
- "rx_q%u_%s", j,
- hns3_rxq_dfx_stats_strings[i].name);
+ "rx_q%u_%s", i,
+ hns3_rxq_dfx_stats_strings[j].name);
(*count)++;
}
}
- for (j = 0; j < dev->data->nb_tx_queues; j++) {
- for (i = 0; i < HNS3_NUM_TXQ_DFX_XSTATS; i++) {
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ for (j = 0; j < HNS3_NUM_TXQ_DFX_XSTATS; j++) {
snprintf(xstats_names[*count].name,
sizeof(xstats_names[*count].name),
- "tx_q%u_%s", j,
- hns3_txq_dfx_stats_strings[i].name);
+ "tx_q%u_%s", i,
+ hns3_txq_dfx_stats_strings[j].name);
(*count)++;
}
}
if (xstats_names == NULL)
return cnt_stats;
+ hns3_tqp_basic_stats_name_get(dev, xstats_names, &count);
+
/* Note: size limited checked in rte_eth_xstats_get_names() */
if (!hns->is_vf) {
/* Get MAC name from hw->hw_xstats.mac_stats struct */
count++;
}
+ for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) {
+ snprintf(xstats_names[count].name,
+ sizeof(xstats_names[count].name),
+ "%s", hns3_imissed_stats_strings[i].name);
+ count++;
+ }
+
for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) {
snprintf(xstats_names[count].name,
sizeof(xstats_names[count].name),
uint32_t count_value;
uint64_t len;
uint32_t i;
- int ret;
if (ids == NULL && values == NULL)
return cnt_stats;
if (size < cnt_stats)
return cnt_stats;
- /* Update tqp stats by read register */
- ret = hns3_update_tqp_stats(hw);
- if (ret) {
- hns3_err(hw, "Update tqp stats fail : %d", ret);
- return ret;
- }
-
len = cnt_stats * sizeof(struct rte_eth_xstat);
values_copy = rte_zmalloc("hns3_xstats_values", len, 0);
if (values_copy == NULL) {
if (ret)
return ret;
+ hns3_tqp_dfx_stats_clear(dev);
+
/* Clear reset stats */
memset(&hns->hw.reset.stats, 0, sizeof(struct hns3_reset_stats));
- hns3_tqp_dfx_stats_clear(dev);
-
if (hns->is_vf)
return 0;
git.droids-corp.org / dpdk.git / blobdiff