net/mlx5: add OS specific flow type selection

[dpdk.git] / drivers / net / i40e / base / i40e_adminq_cmd.h

diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
index d718c73..1905167 100644 (file)
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2018
+ * Copyright(c) 2001-2020 Intel Corporation
  */
 
 #ifndef _I40E_ADMINQ_CMD_H_
@@ -12,8 +12,8 @@
  */
 
 #define I40E_FW_API_VERSION_MAJOR      0x0001
-#define I40E_FW_API_VERSION_MINOR_X722 0x0006
-#define I40E_FW_API_VERSION_MINOR_X710 0x0007
+#define I40E_FW_API_VERSION_MINOR_X722 0x000A
+#define I40E_FW_API_VERSION_MINOR_X710 0x000A
 
 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
                                        I40E_FW_API_VERSION_MINOR_X710 : \
@@ -21,6 +21,8 @@
 
 /* API version 1.7 implements additional link and PHY-specific APIs  */
 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
+/* API version 1.9 for X722 implements additional link and PHY-specific APIs */
+#define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
 
@@ -1402,6 +1404,9 @@ struct i40e_aqc_cloud_filters_element_data {
 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC                 0x000A
 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC     0x000B
 #define I40E_AQC_ADD_CLOUD_FILTER_IIP                  0x000C
+/* 0x000D reserved */
+/* 0x000E reserved */
+/* 0x000F reserved */
 /* 0x0010 to 0x0017 is for custom filters */
 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT              0x0010 /* Dest IP + L4 Port */
 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT             0x0011 /* Dest MAC + L4 Port */
@@ -2098,20 +2103,21 @@ I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
 struct i40e_aq_set_mac_config {
        __le16  max_frame_size;
        u8      params;
-#define I40E_AQ_SET_MAC_CONFIG_CRC_EN          0x04
-#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK     0x78
-#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT    3
-#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE     0x0
-#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX  0xF
-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX  0x9
-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX  0x8
-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX  0x7
-#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX  0x6
-#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX  0x5
-#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX  0x4
-#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX  0x3
-#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX  0x2
-#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX  0x1
+#define I40E_AQ_SET_MAC_CONFIG_CRC_EN                  0x04
+#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK             0x78
+#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT            3
+#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE             0x0
+#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX          0xF
+#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX          0x9
+#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX          0x8
+#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX          0x7
+#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX          0x6
+#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX          0x5
+#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX          0x4
+#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX          0x3
+#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX          0x2
+#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX          0x1
+#define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80
        u8      tx_timer_priority; /* bitmap */
        __le16  tx_timer_value;
        __le16  fc_refresh_threshold;
@@ -2310,7 +2316,11 @@ struct i40e_aqc_phy_register_access {
 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
        u8      dev_addres;
        u8      cmd_flags;
-#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE   1
+#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE   0x01
+#define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER      0x02
+#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT    2
+#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK     (0x3 << \
+               I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
        u8      reserved1;
        __le32  reg_address;
        __le32  reg_value;