* Copyright(c) 2001-2020 Intel Corporation
*/
+#include <inttypes.h>
+
#include "i40e_type.h"
#include "i40e_adminq.h"
#include "i40e_prototype.h"
return status;
}
+/**
+ * i40e_hw_ver_ge
+ * @hw: pointer to the hw struct
+ * @maj: api major value
+ * @min: api minor value
+ *
+ * Assert whether current HW api version is greater/equal than provided.
+ **/
+static bool i40e_hw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min)
+{
+ if (hw->aq.api_maj_ver > maj ||
+ (hw->aq.api_maj_ver == maj && hw->aq.api_min_ver >= min))
+ return true;
+ return false;
+}
+
/**
* i40e_aq_add_vsi
* @hw: pointer to the hw struct
if (set) {
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
- if (rx_only_promisc &&
- (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
- (hw->aq.api_maj_ver > 1)))
- flags |= I40E_AQC_SET_VSI_PROMISC_TX;
+ if (rx_only_promisc && i40e_hw_ver_ge(hw, 1, 5))
+ flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
}
cmd->promiscuous_flags = CPU_TO_LE16(flags);
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
- if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
- (hw->aq.api_maj_ver > 1))
- cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
+ if (i40e_hw_ver_ge(hw, 1, 5))
+ cmd->valid_flags |=
+ CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
cmd->seid = CPU_TO_LE16(seid);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_vsi_promiscuous_modes);
- if (enable)
+ if (enable) {
flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
+ if (i40e_hw_ver_ge(hw, 1, 5))
+ flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
+ }
cmd->promiscuous_flags = CPU_TO_LE16(flags);
cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
+ if (i40e_hw_ver_ge(hw, 1, 5))
+ cmd->valid_flags |=
+ CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
cmd->seid = CPU_TO_LE16(seid);
cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
return status;
}
+/**
+ * i40e_aq_nvm_update_in_process
+ * @hw: pointer to the hw struct
+ * @update_flow_state: True indicates that update flow starts, false that ends
+ * @cmd_details: pointer to command details structure or NULL
+ *
+ * Indicate NVM update in process.
+ **/
+enum i40e_status_code
+i40e_aq_nvm_update_in_process(struct i40e_hw *hw,
+ bool update_flow_state,
+ struct i40e_asq_cmd_details *cmd_details)
+{
+ struct i40e_aq_desc desc;
+ struct i40e_aqc_nvm_update_in_process *cmd =
+ (struct i40e_aqc_nvm_update_in_process *)&desc.params.raw;
+ enum i40e_status_code status;
+
+ i40e_fill_default_direct_cmd_desc(&desc,
+ i40e_aqc_opc_nvm_update_in_process);
+
+ cmd->command = I40E_AQ_UPDATE_FLOW_END;
+
+ if (update_flow_state)
+ cmd->command |= I40E_AQ_UPDATE_FLOW_START;
+
+ status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
+
+ return status;
+}
+
+/**
+ * i40e_aq_min_rollback_rev_update - triggers an ow after update
+ * @hw: pointer to the hw struct
+ * @mode: opt-in mode, 1b for single module update, 0b for bulk update
+ * @module: module to be updated. Ignored if mode is 0b
+ * @min_rrev: value of the new minimal version. Ignored if mode is 0b
+ * @cmd_details: pointer to command details structure or NULL
+ **/
+enum i40e_status_code
+i40e_aq_min_rollback_rev_update(struct i40e_hw *hw, u8 mode, u8 module,
+ u32 min_rrev,
+ struct i40e_asq_cmd_details *cmd_details)
+{
+ struct i40e_aq_desc desc;
+ struct i40e_aqc_rollback_revision_update *cmd =
+ (struct i40e_aqc_rollback_revision_update *)&desc.params.raw;
+ enum i40e_status_code status;
+
+ i40e_fill_default_direct_cmd_desc(&desc,
+ i40e_aqc_opc_rollback_revision_update);
+ cmd->optin_mode = mode;
+ cmd->module_selected = module;
+ cmd->min_rrev = min_rrev;
+
+ status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
+
+ return status;
+}
+
/**
* i40e_aq_oem_post_update - triggers an OEM specific flow after update
* @hw: pointer to the hw struct
p->wr_csr_prot = (u64)number;
p->wr_csr_prot |= (u64)logical_id << 32;
i40e_debug(hw, I40E_DEBUG_INIT,
- "HW Capability: wr_csr_prot = 0x%llX\n\n",
+ "HW Capability: wr_csr_prot = 0x%" PRIX64 "\n\n",
(p->wr_csr_prot & 0xffff));
break;
+ case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
+ p->dis_unused_ports = (bool)number;
+ i40e_debug(hw, I40E_DEBUG_INIT,
+ "HW Capability: dis_unused_ports = %d\n\n",
+ p->dis_unused_ports);
+ break;
case I40E_AQ_CAP_ID_NVM_MGMT:
if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
p->sec_rev_disabled = true;
return status;
}
-/**
- * i40e_aq_nvm_progress
- * @hw: pointer to the hw struct
- * @progress: pointer to progress returned from AQ
- * @cmd_details: pointer to command details structure or NULL
- *
- * Gets progress of flash rearrangement process
- **/
-enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
- struct i40e_asq_cmd_details *cmd_details)
-{
- enum i40e_status_code status;
- struct i40e_aq_desc desc;
-
- DEBUGFUNC("i40e_aq_nvm_progress");
-
- i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
- status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
- *progress = desc.params.raw[0];
- return status;
-}
-
/**
* i40e_aq_get_lldp_mib
* @hw: pointer to the hw struct
/* Cache current configuration */
config.phy_type = abilities.phy_type;
+ config.phy_type_ext = abilities.phy_type_ext;
config.link_speed = abilities.link_speed;
config.abilities = abilities.abilities |
I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
struct i40e_hw_port_stats *stat)
{
enum i40e_status_code ret = I40E_SUCCESS;
+ bool eee_mrvl_phy;
+ bool eee_bcm_phy;
u32 val;
stat->rx_lpi_status = 0;
stat->tx_lpi_status = 0;
- if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
- hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
- (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
- hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
+ eee_bcm_phy =
+ (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
+ hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
+ (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
+ hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB);
+ eee_mrvl_phy =
+ hw->device_id == I40E_DEV_ID_1G_BASE_T_X722;
+
+ if (eee_bcm_phy || eee_mrvl_phy) {
+ /* read Clause 45 PCS Status 1 register */
ret = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
I40E_BCM_PHY_PCS_STATUS1_PAGE,
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