* Copyright(c) 2001-2020 Intel Corporation
*/
+#include <inttypes.h>
+
#include "i40e_type.h"
#include "i40e_adminq.h"
#include "i40e_prototype.h"
p->wr_csr_prot = (u64)number;
p->wr_csr_prot |= (u64)logical_id << 32;
i40e_debug(hw, I40E_DEBUG_INIT,
- "HW Capability: wr_csr_prot = 0x%llX\n\n",
+ "HW Capability: wr_csr_prot = 0x%" PRIX64 "\n\n",
(p->wr_csr_prot & 0xffff));
break;
case I40E_AQ_CAP_ID_DIS_UNUSED_PORTS:
/* Cache current configuration */
config.phy_type = abilities.phy_type;
+ config.phy_type_ext = abilities.phy_type_ext;
config.link_speed = abilities.link_speed;
config.abilities = abilities.abilities |
I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
struct i40e_hw_port_stats *stat)
{
enum i40e_status_code ret = I40E_SUCCESS;
+ bool eee_mrvl_phy;
+ bool eee_bcm_phy;
u32 val;
stat->rx_lpi_status = 0;
stat->tx_lpi_status = 0;
- if ((hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
- hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
- (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
- hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB)) {
+ eee_bcm_phy =
+ (hw->device_id == I40E_DEV_ID_10G_BASE_T_BC ||
+ hw->device_id == I40E_DEV_ID_5G_BASE_T_BC) &&
+ (hw->phy.link_info.link_speed == I40E_LINK_SPEED_2_5GB ||
+ hw->phy.link_info.link_speed == I40E_LINK_SPEED_5GB);
+ eee_mrvl_phy =
+ hw->device_id == I40E_DEV_ID_1G_BASE_T_X722;
+
+ if (eee_bcm_phy || eee_mrvl_phy) {
+ /* read Clause 45 PCS Status 1 register */
ret = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
I40E_BCM_PHY_PCS_STATUS1_PAGE,