mempool: remove macro to check if contiguous

[dpdk.git] / drivers / net / i40e / base / i40e_common.c

diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index e94f726..ef3425e 100644 (file)
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -5356,7 +5356,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
                return ret;
 
        /* Read the PF Queue Filter control register */
-       val = rd32(hw, I40E_PFQF_CTL_0);
+       val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 
        /* Program required PE hash buckets for the PF */
        val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
@@ -5393,7 +5393,7 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
        if (settings->enable_macvlan)
                val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
 
-       wr32(hw, I40E_PFQF_CTL_0, val);
+       i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 
        return I40E_SUCCESS;
 }
@@ -6317,6 +6317,128 @@ restore_config:
        return status;
 }
 #endif /* PF_DRIVER */
+
+/**
+ * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
+ * @hw: pointer to the hw struct
+ * @reg_addr: register address
+ * @reg_val: ptr to register value
+ * @cmd_details: pointer to command details structure or NULL
+ *
+ * Use the firmware to read the Rx control register,
+ * especially useful if the Rx unit is under heavy pressure
+ **/
+enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
+                               u32 reg_addr, u32 *reg_val,
+                               struct i40e_asq_cmd_details *cmd_details)
+{
+       struct i40e_aq_desc desc;
+       struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
+               (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
+       enum i40e_status_code status;
+
+       if (reg_val == NULL)
+               return I40E_ERR_PARAM;
+
+       i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
+
+       cmd_resp->address = CPU_TO_LE32(reg_addr);
+
+       status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
+
+       if (status == I40E_SUCCESS)
+               *reg_val = LE32_TO_CPU(cmd_resp->value);
+
+       return status;
+}
+
+/**
+ * i40e_read_rx_ctl - read from an Rx control register
+ * @hw: pointer to the hw struct
+ * @reg_addr: register address
+ **/
+u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
+{
+       enum i40e_status_code status = I40E_SUCCESS;
+       bool use_register;
+       int retry = 5;
+       u32 val = 0;
+
+       use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
+       if (!use_register) {
+do_retry:
+               status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
+               if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
+                       i40e_msec_delay(1);
+                       retry--;
+                       goto do_retry;
+               }
+       }
+
+       /* if the AQ access failed, try the old-fashioned way */
+       if (status || use_register)
+               val = rd32(hw, reg_addr);
+
+       return val;
+}
+
+/**
+ * i40e_aq_rx_ctl_write_register
+ * @hw: pointer to the hw struct
+ * @reg_addr: register address
+ * @reg_val: register value
+ * @cmd_details: pointer to command details structure or NULL
+ *
+ * Use the firmware to write to an Rx control register,
+ * especially useful if the Rx unit is under heavy pressure
+ **/
+enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
+                               u32 reg_addr, u32 reg_val,
+                               struct i40e_asq_cmd_details *cmd_details)
+{
+       struct i40e_aq_desc desc;
+       struct i40e_aqc_rx_ctl_reg_read_write *cmd =
+               (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
+       enum i40e_status_code status;
+
+       i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
+
+       cmd->address = CPU_TO_LE32(reg_addr);
+       cmd->value = CPU_TO_LE32(reg_val);
+
+       status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
+
+       return status;
+}
+
+/**
+ * i40e_write_rx_ctl - write to an Rx control register
+ * @hw: pointer to the hw struct
+ * @reg_addr: register address
+ * @reg_val: register value
+ **/
+void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
+{
+       enum i40e_status_code status = I40E_SUCCESS;
+       bool use_register;
+       int retry = 5;
+
+       use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
+       if (!use_register) {
+do_retry:
+               status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
+                                                      reg_val, NULL);
+               if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
+                       i40e_msec_delay(1);
+                       retry--;
+                       goto do_retry;
+               }
+       }
+
+       /* if the AQ access failed, try the old-fashioned way */
+       if (status || use_register)
+               wr32(hw, reg_addr, reg_val);
+}
 #ifdef VF_DRIVER
 
 /**