net/mlx5: fix dynamic inline hint handling

[dpdk.git] / drivers / net / i40e / base / i40e_type.h

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index fcdf0eb..014a4c1 100644 (file)
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2018
+ * Copyright(c) 2001-2020 Intel Corporation
  */
 
 #ifndef _I40E_TYPE_H_
@@ -38,7 +38,7 @@
 #define I40E_MAX_PF_VSI                        64
 #define I40E_MAX_PF_QP                 128
 #define I40E_MAX_VSI_QP                        16
-#define I40E_MAX_VF_VSI                        3
+#define I40E_MAX_VF_VSI                        4
 #define I40E_MAX_CHAINED_RX_BUFFERS    5
 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS  16
 
@@ -79,8 +79,8 @@ typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
 #define I40E_HI_BYTE(x)                ((u8)(((x) >> 8) & 0xFF))
 #define I40E_LO_BYTE(x)                ((u8)((x) & 0xFF))
 
-/* Number of Transmit Descriptors must be a multiple of 8. */
-#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE        8
+/* Number of Transmit Descriptors must be a multiple of 32. */
+#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE        32
 /* Number of Receive Descriptors must be a multiple of 32 if
  * the number of descriptors is greater than 32.
  */
@@ -742,6 +742,9 @@ struct i40e_hw {
 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE     BIT_ULL(4)
+#define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)
+#define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
+#define I40E_HW_FLAG_DROP_MODE             BIT_ULL(7)
        u64 flags;
 
        /* Used in set switch config AQ command */
@@ -1495,6 +1498,8 @@ struct i40e_hw_port_stats {
        u32 rx_lpi_status;
        u64 tx_lpi_count;               /* etlpic */
        u64 rx_lpi_count;               /* erlpic */
+       u64 tx_lpi_duration;
+       u64 rx_lpi_duration;
 };
 
 /* Checksum and Shadow RAM pointers */
@@ -2037,4 +2042,10 @@ struct i40e_profile_info {
        u8 reserved[7];
        u8 name[I40E_DDP_NAME_SIZE];
 };
+
+#define I40E_BCM_PHY_PCS_STATUS1_PAGE  0x3
+#define I40E_BCM_PHY_PCS_STATUS1_REG   0x0001
+#define I40E_BCM_PHY_PCS_STATUS1_RX_LPI        BIT(8)
+#define I40E_BCM_PHY_PCS_STATUS1_TX_LPI        BIT(9)
+
 #endif /* _I40E_TYPE_H_ */