net/i40e/base: enable AQ event get in NVM update

[dpdk.git] / drivers / net / i40e / base / i40e_type.h

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 9d7b1a2..056ca4d 100644 (file)
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -77,6 +77,9 @@ POSSIBILITY OF SUCH DAMAGE.
 /* Max default timeout in ms, */
 #define I40E_MAX_NVM_TIMEOUT           18000
 
+/* Max timeout in ms for the phy to respond */
+#define I40E_MAX_PHY_TIMEOUT           500
+
 /* Check whether address is multicast. */
 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
 
@@ -351,6 +354,10 @@ struct i40e_phy_info {
                                             I40E_PHY_TYPE_OFFSET)
 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
                                             I40E_PHY_TYPE_OFFSET)
+#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
+                                            I40E_PHY_TYPE_OFFSET)
+#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
+                                            I40E_PHY_TYPE_OFFSET)
 #define I40E_HW_CAP_MAX_GPIO                   30
 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO                0
 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C         1
@@ -483,6 +490,7 @@ enum i40e_nvmupd_cmd {
        I40E_NVMUPD_STATUS,
        I40E_NVMUPD_EXEC_AQ,
        I40E_NVMUPD_GET_AQ_RESULT,
+       I40E_NVMUPD_GET_AQ_EVENT,
 };
 
 enum i40e_nvmupd_state {
@@ -502,15 +510,21 @@ enum i40e_nvmupd_state {
 
 #define I40E_NVM_MOD_PNT_MASK 0xFF
 
-#define I40E_NVM_TRANS_SHIFT   8
-#define I40E_NVM_TRANS_MASK    (0xf << I40E_NVM_TRANS_SHIFT)
-#define I40E_NVM_CON           0x0
-#define I40E_NVM_SNT           0x1
-#define I40E_NVM_LCB           0x2
-#define I40E_NVM_SA            (I40E_NVM_SNT | I40E_NVM_LCB)
-#define I40E_NVM_ERA           0x4
-#define I40E_NVM_CSUM          0x8
-#define I40E_NVM_EXEC          0xf
+#define I40E_NVM_TRANS_SHIFT                   8
+#define I40E_NVM_TRANS_MASK                    (0xf << I40E_NVM_TRANS_SHIFT)
+#define I40E_NVM_PRESERVATION_FLAGS_SHIFT      12
+#define I40E_NVM_PRESERVATION_FLAGS_MASK \
+                               (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
+#define I40E_NVM_PRESERVATION_FLAGS_SELECTED   0x01
+#define I40E_NVM_PRESERVATION_FLAGS_ALL                0x02
+#define I40E_NVM_CON                           0x0
+#define I40E_NVM_SNT                           0x1
+#define I40E_NVM_LCB                           0x2
+#define I40E_NVM_SA                            (I40E_NVM_SNT | I40E_NVM_LCB)
+#define I40E_NVM_ERA                           0x4
+#define I40E_NVM_CSUM                          0x8
+#define I40E_NVM_AQE                           0xe
+#define I40E_NVM_EXEC                          0xf
 
 #define I40E_NVM_ADAPT_SHIFT   16
 #define I40E_NVM_ADAPT_MASK    (0xffffULL << I40E_NVM_ADAPT_SHIFT)
@@ -526,6 +540,19 @@ struct i40e_nvm_access {
        u8 data[1];
 };
 
+/* (Q)SFP module access definitions */
+#define I40E_I2C_EEPROM_DEV_ADDR       0xA0
+#define I40E_I2C_EEPROM_DEV_ADDR2      0xA2
+#define I40E_MODULE_TYPE_ADDR          0x00
+#define I40E_MODULE_REVISION_ADDR      0x01
+#define I40E_MODULE_SFF_8472_COMP      0x5E
+#define I40E_MODULE_SFF_8472_SWAP      0x5C
+#define I40E_MODULE_SFF_ADDR_MODE      0x04
+#define I40E_MODULE_SFF_DIAG_CAPAB     0x40
+#define I40E_MODULE_TYPE_QSFP_PLUS     0x0D
+#define I40E_MODULE_TYPE_QSFP28                0x11
+#define I40E_MODULE_QSFP_MAX_LEN       640
+
 /* PCI bus types */
 enum i40e_bus_type {
        i40e_bus_type_unknown = 0,
@@ -680,6 +707,7 @@ struct i40e_hw {
        /* state of nvm update process */
        enum i40e_nvmupd_state nvmupd_state;
        struct i40e_aq_desc nvm_wb_desc;
+       struct i40e_aq_desc nvm_aq_event_desc;
        struct i40e_virt_mem nvm_buff;
        bool nvm_release_on_done;
        u16 nvm_wait_opcode;
@@ -702,6 +730,7 @@ struct i40e_hw {
 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
+#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
        u64 flags;
 
        /* Used in set switch config AQ command */
@@ -1918,8 +1947,10 @@ struct i40e_generic_seg_header {
 struct i40e_metadata_segment {
        struct i40e_generic_seg_header header;
        struct i40e_ddp_version version;
+#define I40E_DDP_TRACKID_RDONLY                0
+#define I40E_DDP_TRACKID_INVALID       0xFFFFFFFF
        u32 track_id;
-       char     name[I40E_DDP_NAME_SIZE];
+       char name[I40E_DDP_NAME_SIZE];
 };
 
 struct i40e_device_id_entry {
@@ -1946,15 +1977,36 @@ struct i40e_profile_section_header {
        struct {
 #define SECTION_TYPE_INFO      0x00000010
 #define SECTION_TYPE_MMIO      0x00000800
+#define SECTION_TYPE_RB_MMIO   0x00001800
 #define SECTION_TYPE_AQ                0x00000801
+#define SECTION_TYPE_RB_AQ     0x00001801
 #define SECTION_TYPE_NOTE      0x80000000
 #define SECTION_TYPE_NAME      0x80000001
+#define SECTION_TYPE_PROTO     0x80000002
+#define SECTION_TYPE_PCTYPE    0x80000003
+#define SECTION_TYPE_PTYPE     0x80000004
                u32 type;
                u32 offset;
                u32 size;
        } section;
 };
 
+struct i40e_profile_tlv_section_record {
+       u8 rtype;
+       u8 type;
+       u16 len;
+       u8 data[12];
+};
+
+/* Generic AQ section in proflie */
+struct i40e_profile_aq_section {
+       u16 opcode;
+       u16 flags;
+       u8  param[16];
+       u16 datalen;
+       u8  data[1];
+};
+
 struct i40e_profile_info {
        u32 track_id;
        struct i40e_ddp_version version;