i40e/base: get OEM version

[dpdk.git] / drivers / net / i40e / base / i40e_type.h

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index d9dc59f..4ea9c2d 100644 (file)
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -237,6 +237,24 @@ struct i40e_link_status {
        bool crc_enable;
        u8 pacing;
        u8 requested_speeds;
+       u8 module_type[3];
+       /* 1st byte: module identifier */
+#define I40E_MODULE_TYPE_SFP           0x03
+#define I40E_MODULE_TYPE_QSFP          0x0D
+       /* 2nd byte: ethernet compliance codes for 10/40G */
+#define I40E_MODULE_TYPE_40G_ACTIVE    0x01
+#define I40E_MODULE_TYPE_40G_LR4       0x02
+#define I40E_MODULE_TYPE_40G_SR4       0x04
+#define I40E_MODULE_TYPE_40G_CR4       0x08
+#define I40E_MODULE_TYPE_10G_BASE_SR   0x10
+#define I40E_MODULE_TYPE_10G_BASE_LR   0x20
+#define I40E_MODULE_TYPE_10G_BASE_LRM  0x40
+#define I40E_MODULE_TYPE_10G_BASE_ER   0x80
+       /* 3rd byte: ethernet compliance codes for 1G */
+#define I40E_MODULE_TYPE_1000BASE_SX   0x01
+#define I40E_MODULE_TYPE_1000BASE_LX   0x02
+#define I40E_MODULE_TYPE_1000BASE_CX   0x04
+#define I40E_MODULE_TYPE_1000BASE_T    0x08
 };
 
 struct i40e_phy_info {
@@ -327,6 +345,7 @@ struct i40e_nvm_info {
        bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
        u16 version;              /* NVM package version */
        u32 eetrack;              /* NVM data version */
+       u32 oem_ver;              /* OEM version info */
 };
 
 /* definitions used in NVM update support */
@@ -345,12 +364,17 @@ enum i40e_nvmupd_cmd {
        I40E_NVMUPD_CSUM_CON,
        I40E_NVMUPD_CSUM_SA,
        I40E_NVMUPD_CSUM_LCB,
+       I40E_NVMUPD_STATUS,
+       I40E_NVMUPD_EXEC_AQ,
+       I40E_NVMUPD_GET_AQ_RESULT,
 };
 
 enum i40e_nvmupd_state {
        I40E_NVMUPD_STATE_INIT,
        I40E_NVMUPD_STATE_READING,
-       I40E_NVMUPD_STATE_WRITING
+       I40E_NVMUPD_STATE_WRITING,
+       I40E_NVMUPD_STATE_INIT_WAIT,
+       I40E_NVMUPD_STATE_WRITE_WAIT,
 };
 
 /* nvm_access definition and its masks/shifts need to be accessible to
@@ -369,6 +393,7 @@ enum i40e_nvmupd_state {
 #define I40E_NVM_SA            (I40E_NVM_SNT | I40E_NVM_LCB)
 #define I40E_NVM_ERA           0x4
 #define I40E_NVM_CSUM          0x8
+#define I40E_NVM_EXEC          0xf
 
 #define I40E_NVM_ADAPT_SHIFT   16
 #define I40E_NVM_ADAPT_MASK    (0xffffULL << I40E_NVM_ADAPT_SHIFT)
@@ -531,6 +556,8 @@ struct i40e_hw {
 
        /* state of nvm update process */
        enum i40e_nvmupd_state nvmupd_state;
+       struct i40e_aq_desc nvm_wb_desc;
+       struct i40e_virt_mem nvm_buff;
 
        /* HMC info */
        struct i40e_hmc_info hmc; /* HMC info struct */
@@ -1275,6 +1302,7 @@ struct i40e_hw_port_stats {
 #define I40E_SR_PBA_FLAGS                      0x15
 #define I40E_SR_PBA_BLOCK_PTR                  0x16
 #define I40E_SR_BOOT_CONFIG_PTR                        0x17
+#define I40E_NVM_OEM_VER_OFF                   0x83
 #define I40E_SR_NVM_DEV_STARTER_VERSION                0x18
 #define I40E_SR_NVM_WAKE_ON_LAN                        0x19
 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR  0x27