i40e/base: fix driver load failure

[dpdk.git] / drivers / net / i40e / base / i40e_type.h

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 1cf6965..61ee166 100644 (file)
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -157,6 +157,22 @@ enum i40e_debug_mask {
 #define I40E_PCI_LINK_SPEED_5000       0x2
 #define I40E_PCI_LINK_SPEED_8000       0x3
 
+#define I40E_MDIO_STCODE               0
+#define I40E_MDIO_OPCODE_ADDRESS       0
+#define I40E_MDIO_OPCODE_WRITE         I40E_MASK(1, \
+                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
+#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
+                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
+#define I40E_MDIO_OPCODE_READ          I40E_MASK(3, \
+                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
+
+#define I40E_PHY_COM_REG_PAGE                  0x1E
+#define I40E_PHY_LED_LINK_MODE_MASK            0xF0
+#define I40E_PHY_LED_MANUAL_ON                 0x100
+#define I40E_PHY_LED_PROV_REG_1                        0xC430
+#define I40E_PHY_LED_MODE_MASK                 0xFFFF
+#define I40E_PHY_LED_MODE_ORIG                 0x80000000
+
 /* Memory types */
 enum i40e_memset_type {
        I40E_NONDMA_MEM = 0,
@@ -321,6 +337,17 @@ struct i40e_phy_info {
 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO                0
 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C         1
 
+#ifdef X722_SUPPORT
+enum i40e_acpi_programming_method {
+       I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
+       I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
+};
+
+#define I40E_WOL_SUPPORT_MASK                  1
+#define I40E_ACPI_PROGRAMMING_METHOD_MASK      (1 << 1)
+#define I40E_PROXY_SUPPORT_MASK                        (1 << 2)
+
+#endif
 /* Capabilities of a PF or a VF or the whole device */
 struct i40e_hw_capabilities {
        u32  switch_mode;
@@ -378,6 +405,12 @@ struct i40e_hw_capabilities {
        u8 rx_buf_chain_len;
        u32 enabled_tcmap;
        u32 maxtc;
+       u64 wr_csr_prot;
+#ifdef X722_SUPPORT
+       bool apm_wol_support;
+       enum i40e_acpi_programming_method acpi_prog_method;
+       bool proxy_support;
+#endif
 };
 
 struct i40e_mac_info {
@@ -635,6 +668,15 @@ struct i40e_hw {
        struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
        struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 
+#ifdef X722_SUPPORT
+       /* WoL and proxy support */
+       u16 num_wol_proxy_filters;
+       u16 wol_proxy_vsi_seid;
+
+#endif
+#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
+       u64 flags;
+
        /* debug mask */
        u32 debug_mask;
 #ifndef I40E_NDIS_SUPPORT
@@ -753,7 +795,11 @@ enum i40e_rx_desc_status_bits {
        I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
        I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
        I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
+#ifdef X722_SUPPORT
+       I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
+#else
        I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
+#endif
 
        I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
        I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
@@ -761,7 +807,11 @@ enum i40e_rx_desc_status_bits {
        I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
        I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
        I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
+#ifdef X722_SUPPORT
+       I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
+#else
        I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
+#endif
        I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 };
 
@@ -1139,6 +1189,10 @@ enum i40e_tx_ctx_desc_eipt_offload {
 #define I40E_TXD_CTX_QW0_DECTTL_MASK   (0xFULL << \
                                         I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 
+#ifdef X722_SUPPORT
+#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT  23
+#define I40E_TXD_CTX_QW0_L4T_CS_MASK   BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
+#endif
 struct i40e_nop_desc {
        __le64 rsvd;
        __le64 dtype_cmd;