net/ice: support Rx scatter AVX2 vector

[dpdk.git] / drivers / net / i40e / base / i40e_type.h

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 7dde3bf..7ba62cc 100644 (file)
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -329,6 +329,14 @@ struct i40e_phy_info {
                                             I40E_PHY_TYPE_OFFSET)
 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
                                             I40E_PHY_TYPE_OFFSET)
+#ifdef CARLSVILLE_HW
+/* Offset for 2.5G/5G PHY Types value to bit number conversion */
+#define I40E_PHY_TYPE_OFFSET2 (-10)
+#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
+                                            I40E_PHY_TYPE_OFFSET2)
+#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
+                                            I40E_PHY_TYPE_OFFSET2)
+#endif
 #define I40E_HW_CAP_MAX_GPIO                   30
 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO                0
 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C         1
@@ -349,6 +357,16 @@ struct i40e_hw_capabilities {
 #define I40E_NVM_IMAGE_TYPE_CLOUD      0x2
 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD  0x3
 
+       /* Cloud filter modes:
+        * Mode1: Filter on L4 port only
+        * Mode2: Filter for non-tunneled traffic
+        * Mode3: Filter for tunnel traffic
+        */
+#define I40E_CLOUD_FILTER_MODE1        0x6
+#define I40E_CLOUD_FILTER_MODE2        0x7
+#define I40E_CLOUD_FILTER_MODE3        0x8
+#define I40E_SWITCH_MODE_MASK  0xF
+
        u32  management_mode;
        u32  mng_protocols_over_mctp;
 #define I40E_MNG_PROTOCOL_PLDM         0x2
@@ -652,6 +670,7 @@ struct i40e_hw {
        u8 revision_id;
        u8 port;
        bool adapter_stopped;
+       bool adapter_closed;
 
        /* capabilities for entire device and PCI func */
        struct i40e_hw_capabilities dev_caps;
@@ -702,6 +721,7 @@ struct i40e_hw {
 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
+#define I40E_HW_FLAG_FW_LLDP_STOPPABLE     BIT_ULL(4)
        u64 flags;
 
        /* Used in set switch config AQ command */