net/i40e/base: add raw format for 32 bytes Rx description

[dpdk.git] / drivers / net / i40e / base / i40e_type.h

diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 0cbb132..813c1ec 100644 (file)
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2018
+ * Copyright(c) 2001-2020 Intel Corporation
  */
 
 #ifndef _I40E_TYPE_H_
@@ -79,8 +79,8 @@ typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
 #define I40E_HI_BYTE(x)                ((u8)(((x) >> 8) & 0xFF))
 #define I40E_LO_BYTE(x)                ((u8)((x) & 0xFF))
 
-/* Number of Transmit Descriptors must be a multiple of 8. */
-#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE        8
+/* Number of Transmit Descriptors must be a multiple of 32. */
+#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE        32
 /* Number of Receive Descriptors must be a multiple of 32 if
  * the number of descriptors is greater than 32.
  */
@@ -236,6 +236,14 @@ enum i40e_queue_type {
        I40E_QUEUE_TYPE_UNKNOWN
 };
 
+enum i40e_prt_mac_link_speed {
+       I40E_PRT_MAC_LINK_SPEED_100MB = 0,
+       I40E_PRT_MAC_LINK_SPEED_1GB,
+       I40E_PRT_MAC_LINK_SPEED_10GB,
+       I40E_PRT_MAC_LINK_SPEED_40GB,
+       I40E_PRT_MAC_LINK_SPEED_20GB
+};
+
 struct i40e_link_status {
        enum i40e_aq_phy_type phy_type;
        enum i40e_aq_link_speed link_speed;
@@ -329,12 +337,8 @@ struct i40e_phy_info {
                                             I40E_PHY_TYPE_OFFSET)
 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
                                             I40E_PHY_TYPE_OFFSET)
-/* Offset for 2.5G/5G PHY Types value to bit number conversion */
-#define I40E_PHY_TYPE_OFFSET2 (-10)
-#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
-                                            I40E_PHY_TYPE_OFFSET2)
-#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
-                                            I40E_PHY_TYPE_OFFSET2)
+#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
+#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
 #define I40E_HW_CAP_MAX_GPIO                   30
 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO                0
 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C         1
@@ -425,6 +429,7 @@ struct i40e_hw_capabilities {
        u32 enabled_tcmap;
        u32 maxtc;
        u64 wr_csr_prot;
+       bool dis_unused_ports;
        bool apm_wol_support;
        enum i40e_acpi_programming_method acpi_prog_method;
        bool proxy_support;
@@ -742,6 +747,10 @@ struct i40e_hw {
 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE     BIT_ULL(4)
+#define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)
+#define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
+#define I40E_HW_FLAG_DROP_MODE             BIT_ULL(7)
+#define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
        u64 flags;
 
        /* Used in set switch config AQ command */
@@ -808,7 +817,7 @@ union i40e_32byte_rx_desc {
                __le64  rsvd2;
        } read;
        struct {
-               struct {
+               struct i40e_32b_rx_wb_qw0 {
                        struct {
                                union {
                                        __le16 mirroring_status;
@@ -846,6 +855,9 @@ union i40e_32byte_rx_desc {
                        } hi_dword;
                } qword3;
        } wb;  /* writeback */
+       struct {
+               u64 qword[4];
+       } raw;
 };
 
 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT       8
@@ -957,7 +969,8 @@ enum i40e_rx_l2_ptype {
        I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
        I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
        I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
-       I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
+       I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153,
+       I40E_RX_PTYPE_PARSER_ABORTED                    = 255
 };
 
 struct i40e_rx_ptype_decoded {
@@ -1495,6 +1508,8 @@ struct i40e_hw_port_stats {
        u32 rx_lpi_status;
        u64 tx_lpi_count;               /* etlpic */
        u64 rx_lpi_count;               /* erlpic */
+       u64 tx_lpi_duration;
+       u64 rx_lpi_duration;
 };
 
 /* Checksum and Shadow RAM pointers */
@@ -1547,6 +1562,9 @@ struct i40e_hw_port_stats {
 #define I40E_SR_FEATURE_CONFIGURATION_PTR      0x49
 #define I40E_SR_CONFIGURATION_METADATA_PTR     0x4D
 #define I40E_SR_IMMEDIATE_VALUES_PTR           0x4E
+#define I40E_SR_PRESERVATION_RULES_PTR         0x70
+#define I40E_X722_SR_5TH_FREE_PROVISION_AREA_PTR       0x71
+#define I40E_SR_6TH_FREE_PROVISION_AREA_PTR    0x71
 
 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
 #define I40E_SR_VPD_MODULE_MAX_SIZE            1024
@@ -2037,4 +2055,10 @@ struct i40e_profile_info {
        u8 reserved[7];
        u8 name[I40E_DDP_NAME_SIZE];
 };
+
+#define I40E_BCM_PHY_PCS_STATUS1_PAGE  0x3
+#define I40E_BCM_PHY_PCS_STATUS1_REG   0x0001
+#define I40E_BCM_PHY_PCS_STATUS1_RX_LPI        BIT(8)
+#define I40E_BCM_PHY_PCS_STATUS1_TX_LPI        BIT(9)
+
 #endif /* _I40E_TYPE_H_ */