net/i40e/base: remove FPK HyperV VF device ID
[dpdk.git] / drivers / net / i40e / base / i40e_type.h
index b5f72c3..8889fc7 100644 (file)
@@ -157,15 +157,22 @@ enum i40e_debug_mask {
 #define I40E_PCI_LINK_SPEED_5000       0x2
 #define I40E_PCI_LINK_SPEED_8000       0x3
 
-#define I40E_MDIO_STCODE               I40E_MASK(0, \
+#define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
                                                  I40E_GLGEN_MSCA_STCODE_SHIFT)
-#define I40E_MDIO_OPCODE_ADDRESS       I40E_MASK(0, \
+#define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK   I40E_MASK(1, \
                                                  I40E_GLGEN_MSCA_OPCODE_SHIFT)
-#define I40E_MDIO_OPCODE_WRITE         I40E_MASK(1, \
+#define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK    I40E_MASK(2, \
                                                  I40E_GLGEN_MSCA_OPCODE_SHIFT)
-#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
+
+#define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
+                                                 I40E_GLGEN_MSCA_STCODE_SHIFT)
+#define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
+                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
+#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK   I40E_MASK(1, \
+                                                 I40E_GLGEN_MSCA_OPCODE_SHIFT)
+#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK   I40E_MASK(2, \
                                                  I40E_GLGEN_MSCA_OPCODE_SHIFT)
-#define I40E_MDIO_OPCODE_READ          I40E_MASK(3, \
+#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK    I40E_MASK(3, \
                                                  I40E_GLGEN_MSCA_OPCODE_SHIFT)
 
 #define I40E_PHY_COM_REG_PAGE                  0x1E
@@ -205,7 +212,6 @@ enum i40e_memcpy_type {
  */
 enum i40e_mac_type {
        I40E_MAC_UNKNOWN = 0,
-       I40E_MAC_X710,
        I40E_MAC_XL710,
        I40E_MAC_VF,
 #ifdef X722_SUPPORT
@@ -359,6 +365,10 @@ struct i40e_hw_capabilities {
 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD  0x3
 
        u32  management_mode;
+       u32  mng_protocols_over_mctp;
+#define I40E_MNG_PROTOCOL_PLDM         0x2
+#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
+#define I40E_MNG_PROTOCOL_NCSI         0x8
        u32  npar_enable;
        u32  os2bmc;
        u32  valid_functions;
@@ -554,6 +564,7 @@ struct i40e_bus_info {
        u16 func;
        u16 device;
        u16 lan_id;
+       u16 bus_id;
 };
 
 /* Flow control (FC) parameters */