-/*-
- * BSD LICENSE
- *
- * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Intel Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2017 Intel Corporation
*/
#include <stdio.h>
#include <rte_eal.h>
#include <rte_string_fns.h>
#include <rte_pci.h>
+#include <rte_bus_pci.h>
#include <rte_ether.h>
#include <rte_ethdev.h>
#include <rte_ethdev_pci.h>
static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
enum rte_vlan_type vlan_type,
uint16_t tpid);
-static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
+static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
uint16_t queue,
int on);
static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
{
/*
- * Initialize registers for flexible payload, which should be set by NVM.
- * This should be removed from code once it is fixed in NVM.
+ * Force global configuration for flexible payload
+ * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
+ * This should be removed from code once proper
+ * configuration API is added to avoid configuration conflicts
+ * between ports of the same device.
*/
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
- I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
- I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
- I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
- /* Initialize registers for parsing packet type of QinQ */
+ /*
+ * Initialize registers for parsing packet type of QinQ
+ * This should be removed from code once proper
+ * configuration API is added to avoid configuration conflicts
+ * between ports of the same device.
+ */
I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
}
struct rte_hash_parameters fdir_hash_params = {
.name = fdir_hash_name,
.entries = I40E_MAX_FDIR_FILTER_NUM,
- .key_len = sizeof(struct rte_eth_fdir_input),
+ .key_len = sizeof(struct i40e_fdir_input),
.hash_func = rte_hash_crc,
.hash_func_init_val = 0,
.socket_id = rte_socket_id(),
intr_handle = &pci_dev->intr_handle;
rte_eth_copy_pci_info(dev, pci_dev);
- dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
pf->adapter->eth_dev = dev;
/* Write first RX queue to Link list register as the head element */
if (vsi->type != I40E_VSI_SRIOV) {
uint16_t interval =
- i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
+ i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
if (msix_vect == I40E_MISC_VEC_ID) {
I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t interval = i40e_calc_itr_interval(\
- RTE_LIBRTE_I40E_ITR_INTERVAL);
+ RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
uint16_t msix_intr, i;
if (rte_intr_allow_others(intr_handle))
}
}
+ /* Enable mac loopback mode */
+ if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
+ dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
+ ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
+ if (ret != I40E_SUCCESS) {
+ PMD_DRV_LOG(ERR, "fail to set loopback link");
+ goto err_up;
+ }
+ }
+
/* Apply link configure */
if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
return ret;
}
-static void
+static int
i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
else
i40e_vsi_config_double_vlan(vsi, FALSE);
}
+
+ return 0;
}
static void
mem->size = size;
mem->va = mz->addr;
- mem->pa = mz->phys_addr;
+ mem->pa = mz->iova;
mem->zone = (const void *)mz;
PMD_DRV_LOG(DEBUG,
"memzone %s allocated with physical address: %"PRIu64,
int mask = 0;
/* Apply vlan offload setting */
- mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
- i40e_vlan_offload_set(dev, mask);
-
- /* Apply double-vlan setting, not implemented yet */
+ mask = ETH_VLAN_STRIP_MASK |
+ ETH_VLAN_FILTER_MASK |
+ ETH_VLAN_EXTEND_MASK;
+ ret = i40e_vlan_offload_set(dev, mask);
+ if (ret) {
+ PMD_DRV_LOG(INFO, "Failed to update vlan offload");
+ return ret;
+ }
/* Apply pvid setting */
ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
uint8_t add)
{
uint16_t ip_type;
- uint32_t ipv4_addr;
+ uint32_t ipv4_addr, ipv4_addr_le;
uint8_t i, tun_type = 0;
/* internal varialbe to convert ipv6 byte order */
uint32_t convert_ipv6[4];
if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
+ ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
rte_memcpy(&pfilter->element.ipaddr.v4.data,
- &rte_cpu_to_le_32(ipv4_addr),
+ &ipv4_addr_le,
sizeof(pfilter->element.ipaddr.v4.data));
} else {
ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
uint8_t add)
{
uint16_t ip_type;
- uint32_t ipv4_addr;
+ uint32_t ipv4_addr, ipv4_addr_le;
uint8_t i, tun_type = 0;
/* internal variable to convert ipv6 byte order */
uint32_t convert_ipv6[4];
if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
+ ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
rte_memcpy(&pfilter->element.ipaddr.v4.data,
- &rte_cpu_to_le_32(ipv4_addr),
+ &ipv4_addr_le,
sizeof(pfilter->element.ipaddr.v4.data));
} else {
ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
/* For both X710 and XL710 */
#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
-#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
+#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
#define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
#define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t interval =
- i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
+ i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
uint16_t msix_intr;
msix_intr = intr_handle->intr_vec[queue_id];
struct rte_pmd_i40e_proto_info *proto)
{
struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
- uint8_t port_id = dev->data->port_id;
+ uint16_t port_id = dev->data->port_id;
uint32_t ptype_num;
struct rte_pmd_i40e_ptype_info *ptype;
uint32_t buff_size;
uint8_t proto_id;
- char name[16];
+ char name[RTE_PMD_I40E_DDP_NAME_SIZE];
uint32_t i, j, n;
- bool inner_ip;
+ bool in_tunnel;
int ret;
/* get information about new ptype num */
for (i = 0; i < ptype_num; i++) {
ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
ptype_mapping[i].sw_ptype = 0;
- inner_ip = false;
+ in_tunnel = false;
for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
proto_id = ptype[i].protocols[j];
if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
continue;
memset(name, 0, sizeof(name));
strcpy(name, proto[n].name);
- if (!strncmp(name, "IPV4", 4) && !inner_ip) {
+ if (!strncmp(name, "PPPOE", 5))
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_L2_ETHER_PPPOE;
+ else if (!strncmp(name, "OIPV4", 5)) {
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
- inner_ip = true;
+ in_tunnel = true;
} else if (!strncmp(name, "IPV4", 4) &&
- inner_ip) {
+ !in_tunnel)
ptype_mapping[i].sw_ptype |=
- RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
- } else if (!strncmp(name, "IPV6", 4) &&
- !inner_ip) {
+ RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!strncmp(name, "IPV4FRAG", 8) &&
+ in_tunnel) {
ptype_mapping[i].sw_ptype |=
- RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
- inner_ip = true;
- } else if (!strncmp(name, "IPV6", 4) &&
- inner_ip) {
+ RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
ptype_mapping[i].sw_ptype |=
- RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
- } else if (!strncmp(name, "IPV4FRAG", 8)) {
+ RTE_PTYPE_INNER_L4_FRAG;
+ } else if (!strncmp(name, "IPV4", 4) &&
+ in_tunnel)
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else if (!strncmp(name, "OIPV6", 5)) {
ptype_mapping[i].sw_ptype |=
- RTE_PTYPE_INNER_L4_FRAG;
- } else if (!strncmp(name, "IPV6FRAG", 8)) {
+ RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ in_tunnel = true;
+ } else if (!strncmp(name, "IPV6", 4) &&
+ !in_tunnel)
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (!strncmp(name, "IPV6FRAG", 8) &&
+ in_tunnel) {
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L4_FRAG;
- } else if (!strncmp(name, "GTPC", 4))
+ } else if (!strncmp(name, "IPV6", 4) &&
+ in_tunnel)
ptype_mapping[i].sw_ptype |=
- RTE_PTYPE_TUNNEL_GTPC;
- else if (!strncmp(name, "GTPU", 4))
+ RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+ else if (!strncmp(name, "UDP", 3) && !in_tunnel)
ptype_mapping[i].sw_ptype |=
- RTE_PTYPE_TUNNEL_GTPU;
- else if (!strncmp(name, "UDP", 3))
+ RTE_PTYPE_L4_UDP;
+ else if (!strncmp(name, "UDP", 3) && in_tunnel)
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L4_UDP;
- else if (!strncmp(name, "TCP", 3))
+ else if (!strncmp(name, "TCP", 3) && !in_tunnel)
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_L4_TCP;
+ else if (!strncmp(name, "TCP", 3) && in_tunnel)
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L4_TCP;
- else if (!strncmp(name, "SCTP", 4))
+ else if (!strncmp(name, "SCTP", 4) &&
+ !in_tunnel)
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_L4_SCTP;
+ else if (!strncmp(name, "SCTP", 4) && in_tunnel)
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L4_SCTP;
- else if (!strncmp(name, "ICMP", 4) ||
- !strncmp(name, "ICMPV6", 6))
+ else if ((!strncmp(name, "ICMP", 4) ||
+ !strncmp(name, "ICMPV6", 6)) &&
+ !in_tunnel)
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_L4_ICMP;
+ else if ((!strncmp(name, "ICMP", 4) ||
+ !strncmp(name, "ICMPV6", 6)) &&
+ in_tunnel)
ptype_mapping[i].sw_ptype |=
RTE_PTYPE_INNER_L4_ICMP;
+ else if (!strncmp(name, "GTPC", 4)) {
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_TUNNEL_GTPC;
+ in_tunnel = true;
+ } else if (!strncmp(name, "GTPU", 4)) {
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_TUNNEL_GTPU;
+ in_tunnel = true;
+ } else if (!strncmp(name, "GRENAT", 6)) {
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_TUNNEL_GRENAT;
+ in_tunnel = true;
+ } else if (!strncmp(name, "L2TPv2CTL", 9)) {
+ ptype_mapping[i].sw_ptype |=
+ RTE_PTYPE_TUNNEL_L2TP;
+ in_tunnel = true;
+ }
break;
}