(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
(1UL << RTE_ETH_FLOW_L2_PAYLOAD))
-#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
-#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
-#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
-#define I40E_PRTTSYN_TSYNENA 0x80000000
-#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
+/* Additional timesync values. */
+#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
+#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
+#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
+#define I40E_PRTTSYN_TSYNENA 0x80000000
+#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
+#define I40E_CYCLECOUNTER_MASK 0xffffffffffffffff
#define I40E_MAX_PERCENT 100
#define I40E_DEFAULT_DCB_APP_NUM 1
static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
struct rte_eth_xstats *xstats, unsigned n);
static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
-static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
uint16_t queue_id,
uint8_t stat_idx,
static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
struct timespec *timestamp);
static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
+
+static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+
+static int i40e_timesync_read_time(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+static int i40e_timesync_write_time(struct rte_eth_dev *dev,
+ const struct timespec *timestamp);
+
static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
uint16_t queue_id);
static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
uint16_t queue_id);
+
static const struct rte_pci_id pci_id_i40e_map[] = {
#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "rte_pci_dev_ids.h"
.stats_get = i40e_dev_stats_get,
.xstats_get = i40e_dev_xstats_get,
.stats_reset = i40e_dev_stats_reset,
- .xstats_reset = i40e_dev_xstats_reset,
+ .xstats_reset = i40e_dev_stats_reset,
.queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
.dev_infos_get = i40e_dev_info_get,
.vlan_filter_set = i40e_vlan_filter_set,
.timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
.get_dcb_info = i40e_dev_get_dcb_info,
+ .timesync_adjust_time = i40e_timesync_adjust_time,
+ .timesync_read_time = i40e_timesync_read_time,
+ .timesync_write_time = i40e_timesync_write_time,
};
/* store statistics names and its offset in stats structure */
{"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
};
+#define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
+ sizeof(rte_i40e_stats_strings[0]))
+
static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
{"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
tx_dropped_link_down)},
rx_lpi_count)},
};
-/* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
-#define I40E_NB_HW_PORT_Q_STATS (8 * 5)
-
-#define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
- sizeof(rte_i40e_stats_strings[0]))
#define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
sizeof(rte_i40e_hw_port_strings[0]))
-#define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
- I40E_NB_HW_PORT_Q_STATS)
+
+static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
+ {"xon_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xon_rx)},
+ {"xoff_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xoff_rx)},
+};
+
+#define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
+ sizeof(rte_i40e_rxq_prio_strings[0]))
+
+static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
+ {"xon_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xon_tx)},
+ {"xoff_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xoff_tx)},
+ {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xon_2_xoff)},
+};
+
+#define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
+ sizeof(rte_i40e_txq_prio_strings[0]))
static struct eth_driver rte_i40e_pmd = {
.pci_drv = {
}
if (pf->fdir.fdir_vsi) {
- i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
- i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
+ i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
+ i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
}
/* Clear all queues and release memory */
i40e_dev_clear_queues(dev);
stats->oerrors = ns->eth.tx_errors +
pf->main_vsi->eth_stats.tx_errors;
stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
- stats->fdirmatch = ns->fd_sb_match;
/* Rx Errors */
- stats->ibadcrc = ns->crc_errors;
- stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
- ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
stats->imissed = ns->eth.rx_discards +
pf->main_vsi->eth_stats.rx_discards;
- stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
+ stats->ierrors = ns->crc_errors +
+ ns->rx_length_errors + ns->rx_undersize +
+ ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
+ stats->imissed;
PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
}
+/* Reset the statistics */
static void
-i40e_dev_xstats_reset(struct rte_eth_dev *dev)
+i40e_dev_stats_reset(struct rte_eth_dev *dev)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct i40e_hw_port_stats *hw_stats = &pf->stats;
- /* The hw registers are cleared on read */
+ /* Mark PF and VSI stats to update the offset, aka "reset" */
pf->offset_loaded = false;
+ if (pf->main_vsi)
+ pf->main_vsi->offset_loaded = false;
+
+ /* read the stats, reading current register values into offset */
i40e_read_stats_registers(pf, hw);
+}
- /* reset software counters */
- memset(hw_stats, 0, sizeof(*hw_stats));
+static uint32_t
+i40e_xstats_calc_num(void)
+{
+ return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
+ (I40E_NB_RXQ_PRIO_XSTATS * 8) +
+ (I40E_NB_TXQ_PRIO_XSTATS * 8);
}
static int
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- unsigned i, count = 0;
+ unsigned i, count, prio;
struct i40e_hw_port_stats *hw_stats = &pf->stats;
- if (n < I40E_NB_XSTATS)
- return I40E_NB_XSTATS;
+ count = i40e_xstats_calc_num();
+ if (n < count)
+ return count;
i40e_read_stats_registers(pf, hw);
- /* Reset */
if (xstats == NULL)
return 0;
+ count = 0;
+
/* Get stats from i40e_eth_stats struct */
for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
snprintf(xstats[count].name, sizeof(xstats[count].name),
count++;
}
- /* Get per-queue stats from i40e_hw_port struct */
- for (i = 0; i < 8; i++) {
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "rx_q%u_xon_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xon_rx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "rx_q%u_xoff_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xoff_rx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "tx_q%u_xon_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xon_tx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "tx_q%u_xoff_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xoff_tx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "xx_q%u_xon_to_xoff_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xon_2_xoff[i]));
- count++;
+ for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
+ for (prio = 0; prio < 8; prio++) {
+ snprintf(xstats[count].name,
+ sizeof(xstats[count].name),
+ "rx_priority%u_%s", prio,
+ rte_i40e_rxq_prio_strings[i].name);
+ xstats[count].value =
+ *(uint64_t *)(((char *)hw_stats) +
+ rte_i40e_rxq_prio_strings[i].offset +
+ (sizeof(uint64_t) * prio));
+ count++;
+ }
}
- return I40E_NB_XSTATS;
-}
-
-/* Reset the statistics */
-static void
-i40e_dev_stats_reset(struct rte_eth_dev *dev)
-{
- struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
+ for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
+ for (prio = 0; prio < 8; prio++) {
+ snprintf(xstats[count].name,
+ sizeof(xstats[count].name),
+ "tx_priority%u_%s", prio,
+ rte_i40e_txq_prio_strings[i].name);
+ xstats[count].value =
+ *(uint64_t *)(((char *)hw_stats) +
+ rte_i40e_txq_prio_strings[i].offset +
+ (sizeof(uint64_t) * prio));
+ count++;
+ }
+ }
- /* It results in reloading the start point of each counter */
- pf->offset_loaded = false;
+ return count;
}
static int
u64 size,
u32 alignment)
{
- static uint64_t id = 0;
const struct rte_memzone *mz = NULL;
char z_name[RTE_MEMZONE_NAMESIZE];
if (!mem)
return I40E_ERR_PARAM;
- id++;
- snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
-#ifdef RTE_LIBRTE_XEN_DOM0
+ snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
alignment, RTE_PGSIZE_2M);
-#else
- mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
- alignment);
-#endif
if (!mz)
return I40E_ERR_NO_MEMORY;
- mem->id = id;
mem->size = size;
mem->va = mz->addr;
-#ifdef RTE_LIBRTE_XEN_DOM0
mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
-#else
- mem->pa = mz->phys_addr;
-#endif
+ mem->zone = (const void *)mz;
+ PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
+ "%"PRIu64, mz->name, mem->pa);
return I40E_SUCCESS;
}
i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
struct i40e_dma_mem *mem)
{
- if (!mem || !mem->va)
+ if (!mem)
return I40E_ERR_PARAM;
+ PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
+ "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
+ mem->pa);
+ rte_memzone_free((const struct rte_memzone *)mem->zone);
+ mem->zone = NULL;
mem->va = NULL;
mem->pa = (u64)0;
/* VMDq queue/VSI allocation */
pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
+ pf->vmdq_nb_qps = 0;
+ pf->max_nb_vmdq_vsi = 0;
if (hw->func_caps.vmdq) {
- pf->flags |= I40E_FLAG_VMDQ;
- pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
- pf->max_nb_vmdq_vsi = 1;
- PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues per VMDQ VSI, "
- "in total %u queues", pf->max_nb_vmdq_vsi,
- pf->vmdq_nb_qps,
- pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
- } else {
- pf->vmdq_nb_qps = 0;
- pf->max_nb_vmdq_vsi = 0;
+ if (qp_count < hw->func_caps.num_tx_qp &&
+ vsi_count < hw->func_caps.num_vsis) {
+ pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
+ qp_count) / pf->vmdq_nb_qp_max;
+
+ /* Limit the maximum number of VMDq vsi to the maximum
+ * ethdev can support
+ */
+ pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
+ hw->func_caps.num_vsis - vsi_count);
+ pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
+ ETH_64_POOLS);
+ if (pf->max_nb_vmdq_vsi) {
+ pf->flags |= I40E_FLAG_VMDQ;
+ pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
+ PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
+ "per VMDQ VSI, in total %u queues",
+ pf->max_nb_vmdq_vsi,
+ pf->vmdq_nb_qps, pf->vmdq_nb_qps *
+ pf->max_nb_vmdq_vsi);
+ } else {
+ PMD_DRV_LOG(INFO, "No enough queues left for "
+ "VMDq");
+ }
+ } else {
+ PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
+ }
}
qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
vsi_count += pf->max_nb_vmdq_vsi;
return !((src1 ^ src2) & src2);
}
-static int
+static enum i40e_status_code
validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
{
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
/* If DCB is not supported, only default TC is supported */
if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
- return -EINVAL;
+ return I40E_NOT_SUPPORTED;
}
if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
"HW support 0x%x", hw->func_caps.enabled_tcmap,
enabled_tcmap);
- return -EINVAL;
+ return I40E_NOT_SUPPORTED;
}
return I40E_SUCCESS;
}
return I40E_SUCCESS;
}
-static int
+static enum i40e_status_code
i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
struct i40e_aqc_vsi_properties_data *info,
uint8_t enabled_tcmap)
{
- int ret, i, total_tc = 0;
+ enum i40e_status_code ret;
+ int i, total_tc = 0;
uint16_t qpnum_per_tc, bsf, qp_idx;
ret = validate_tcmap_parameter(vsi, enabled_tcmap);
return 0;
}
-static int
-i40e_timesync_enable(struct rte_eth_dev *dev)
+static uint64_t
+i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_eth_link *link = &dev->data->dev_link;
- uint32_t tsync_ctl_l;
- uint32_t tsync_ctl_h;
+ uint64_t systim_cycles;
+
+ systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
+ systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
+ << 32;
+
+ return systim_cycles;
+}
+
+static uint64_t
+i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t rx_tstamp;
+
+ rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
+ rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
+ << 32;
+
+ return rx_tstamp;
+}
+
+static uint64_t
+i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t tx_tstamp;
+
+ tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
+ tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
+ << 32;
+
+ return tx_tstamp;
+}
+
+static void
+i40e_start_timecounters(struct rte_eth_dev *dev)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+ struct rte_eth_link link;
uint32_t tsync_inc_l;
uint32_t tsync_inc_h;
- switch (link->link_speed) {
+ /* Get current link speed. */
+ memset(&link, 0, sizeof(link));
+ i40e_dev_link_update(dev, 1);
+ rte_i40e_dev_atomic_read_link_status(dev, &link);
+
+ switch (link.link_speed) {
case ETH_LINK_SPEED_40G:
tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
tsync_inc_h = 0x0;
}
- /* Clear timesync registers. */
- I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
- I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
- I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
-
/* Set the timesync increment value. */
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
+ memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
+ memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
+ memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
+
+ adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
+ adapter->systime_tc.cc_shift = 0;
+ adapter->systime_tc.nsec_mask = 0;
+
+ adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
+ adapter->rx_tstamp_tc.cc_shift = 0;
+ adapter->rx_tstamp_tc.nsec_mask = 0;
+
+ adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
+ adapter->tx_tstamp_tc.cc_shift = 0;
+ adapter->tx_tstamp_tc.nsec_mask = 0;
+}
+
+static int
+i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
+{
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
+ adapter->systime_tc.nsec += delta;
+ adapter->rx_tstamp_tc.nsec += delta;
+ adapter->tx_tstamp_tc.nsec += delta;
+
+ return 0;
+}
+
+static int
+i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
+{
+ uint64_t ns;
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
+ ns = rte_timespec_to_ns(ts);
+
+ /* Set the timecounters to a new value. */
+ adapter->systime_tc.nsec = ns;
+ adapter->rx_tstamp_tc.nsec = ns;
+ adapter->tx_tstamp_tc.nsec = ns;
+
+ return 0;
+}
+
+static int
+i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
+{
+ uint64_t ns, systime_cycles;
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
+ systime_cycles = i40e_read_systime_cyclecounter(dev);
+ ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
+ *ts = rte_ns_to_timespec(ns);
+
+ return 0;
+}
+
+static int
+i40e_timesync_enable(struct rte_eth_dev *dev)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t tsync_ctl_l;
+ uint32_t tsync_ctl_h;
+
+ /* Stop the timesync system time. */
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
+ /* Reset the timesync system time value. */
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
+
+ i40e_start_timecounters(dev);
+
+ /* Clear timesync registers. */
+ I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
+ I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
+
/* Enable timestamping of PTP packets. */
tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
- /* Set the timesync increment value. */
+ /* Reset the timesync increment value. */
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
struct timespec *timestamp, uint32_t flags)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
uint32_t sync_status;
- uint32_t rx_stmpl;
- uint32_t rx_stmph;
uint32_t index = flags & 0x03;
+ uint64_t rx_tstamp_cycles;
+ uint64_t ns;
sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
if ((sync_status & (1 << index)) == 0)
return -EINVAL;
- rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
- rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
-
- timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
- timestamp->tv_nsec = 0;
+ rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
+ ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
+ *timestamp = rte_ns_to_timespec(ns);
- return 0;
+ return 0;
}
static int
struct timespec *timestamp)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
uint32_t sync_status;
- uint32_t tx_stmpl;
- uint32_t tx_stmph;
+ uint64_t tx_tstamp_cycles;
+ uint64_t ns;
sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
return -EINVAL;
- tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
- tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
-
- timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
- timestamp->tv_nsec = 0;
+ tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
+ ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
+ *timestamp = rte_ns_to_timespec(ns);
- return 0;
+ return 0;
}
/*
*
* Returns 0 on success, negative value on failure
*/
-static int
+static enum i40e_status_code
i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
{
struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
- int i, ret;
+ enum i40e_status_code ret;
+ int i;
uint32_t tc_bw_max;
/* Get the VSI level BW configuration */
"couldn't get PF vsi bw config, err %s aq_err %s\n",
i40e_stat_str(hw, ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
- return -EINVAL;
+ return ret;
}
/* Get the VSI level BW configuration per TC */
"couldn't get PF vsi ets bw config, err %s aq_err %s\n",
i40e_stat_str(hw, ret),
i40e_aq_str(hw, hw->aq.asq_last_status));
- return -EINVAL;
+ return ret;
}
if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
__func__, vsi->seid, i, bw_config.qs_handles[i]);
}
- return 0;
+ return ret;
}
-static int
+static enum i40e_status_code
i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
struct i40e_aqc_vsi_properties_data *info,
uint8_t enabled_tcmap)
{
- int ret, i, total_tc = 0;
+ enum i40e_status_code ret;
+ int i, total_tc = 0;
uint16_t qpnum_per_tc, bsf, qp_idx;
struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
*
* Returns 0 on success, negative value on failure
*/
-static int
+static enum i40e_status_code
i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
{
struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
struct i40e_vsi_context ctxt;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
- int ret = 0;
+ enum i40e_status_code ret = I40E_SUCCESS;
int i;
/* Check if enabled_tc is same as existing or new TCs */
struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
struct i40e_vsi *main_vsi = pf->main_vsi;
struct i40e_vsi_list *vsi_list;
- int i, ret;
+ enum i40e_status_code ret;
+ int i;
uint32_t val;
/* Use the FW API if FW > v4.4*/
git.droids-corp.org / dpdk.git / blobdiff