net/i40e: fix link speed for X722

[dpdk.git] / drivers / net / i40e / i40e_ethdev.c

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 3815aef..2eea523 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -24,7 +24,6 @@
 #include <rte_memcpy.h>
 #include <rte_alarm.h>
 #include <rte_dev.h>
-#include <rte_eth_ctrl.h>
 #include <rte_tailq.h>
 #include <rte_hash_crc.h>
 
@@ -2671,11 +2670,11 @@ update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
 #define I40E_PRTMAC_MACC               0x001E24E0
 #define I40E_REG_MACC_25GB             0x00020000
 #define I40E_REG_SPEED_MASK            0x38000000
-#define I40E_REG_SPEED_100MB           0x00000000
-#define I40E_REG_SPEED_1GB             0x08000000
-#define I40E_REG_SPEED_10GB            0x10000000
-#define I40E_REG_SPEED_20GB            0x20000000
-#define I40E_REG_SPEED_25_40GB         0x18000000
+#define I40E_REG_SPEED_0               0x00000000
+#define I40E_REG_SPEED_1               0x08000000
+#define I40E_REG_SPEED_2               0x10000000
+#define I40E_REG_SPEED_3               0x18000000
+#define I40E_REG_SPEED_4               0x20000000
        uint32_t link_speed;
        uint32_t reg_val;
 
@@ -2689,26 +2688,35 @@ update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
 
        /* Parse the link status */
        switch (link_speed) {
-       case I40E_REG_SPEED_100MB:
+       case I40E_REG_SPEED_0:
                link->link_speed = ETH_SPEED_NUM_100M;
                break;
-       case I40E_REG_SPEED_1GB:
+       case I40E_REG_SPEED_1:
                link->link_speed = ETH_SPEED_NUM_1G;
                break;
-       case I40E_REG_SPEED_10GB:
-               link->link_speed = ETH_SPEED_NUM_10G;
-               break;
-       case I40E_REG_SPEED_20GB:
-               link->link_speed = ETH_SPEED_NUM_20G;
+       case I40E_REG_SPEED_2:
+               if (hw->mac.type == I40E_MAC_X722)
+                       link->link_speed = ETH_SPEED_NUM_2_5G;
+               else
+                       link->link_speed = ETH_SPEED_NUM_10G;
                break;
-       case I40E_REG_SPEED_25_40GB:
-               reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
+       case I40E_REG_SPEED_3:
+               if (hw->mac.type == I40E_MAC_X722) {
+                       link->link_speed = ETH_SPEED_NUM_5G;
+               } else {
+                       reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
 
-               if (reg_val & I40E_REG_MACC_25GB)
-                       link->link_speed = ETH_SPEED_NUM_25G;
+                       if (reg_val & I40E_REG_MACC_25GB)
+                               link->link_speed = ETH_SPEED_NUM_25G;
+                       else
+                               link->link_speed = ETH_SPEED_NUM_40G;
+               }
+               break;
+       case I40E_REG_SPEED_4:
+               if (hw->mac.type == I40E_MAC_X722)
+                       link->link_speed = ETH_SPEED_NUM_10G;
                else
-                       link->link_speed = ETH_SPEED_NUM_40G;
-
+                       link->link_speed = ETH_SPEED_NUM_20G;
                break;
        default:
                PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
@@ -3324,17 +3332,17 @@ static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 
        /* Get stats from i40e_eth_stats struct */
        for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
-               snprintf(xstats_names[count].name,
-                        sizeof(xstats_names[count].name),
-                        "%s", rte_i40e_stats_strings[i].name);
+               strlcpy(xstats_names[count].name,
+                       rte_i40e_stats_strings[i].name,
+                       sizeof(xstats_names[count].name));
                count++;
        }
 
        /* Get individiual stats from i40e_hw_port struct */
        for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
-               snprintf(xstats_names[count].name,
-                       sizeof(xstats_names[count].name),
-                        "%s", rte_i40e_hw_port_strings[i].name);
+               strlcpy(xstats_names[count].name,
+                       rte_i40e_hw_port_strings[i].name,
+                       sizeof(xstats_names[count].name));
                count++;
        }
 
@@ -3499,6 +3507,8 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
        dev_info->max_mac_addrs = vsi->max_macaddrs;
        dev_info->max_vfs = pci_dev->max_vfs;
+       dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
+       dev_info->min_mtu = ETHER_MIN_MTU;
        dev_info->rx_queue_offload_capa = 0;
        dev_info->rx_offload_capa =
                DEV_RX_OFFLOAD_VLAN_STRIP |
@@ -7720,6 +7730,9 @@ i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
        case RTE_TUNNEL_TYPE_IP_IN_GRE:
                tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
                break;
+       case RTE_TUNNEL_TYPE_VXLAN_GPE:
+               tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
+               break;
        default:
                /* Other tunnel types is not supported. */
                PMD_DRV_LOG(ERR, "tunnel type is not supported.");
@@ -8368,7 +8381,7 @@ i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
 }
 
 static int
-i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
+i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
 {
        int  idx, ret;
        uint8_t filter_idx;
@@ -8391,7 +8404,7 @@ i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
                return -ENOSPC;
        }
 
-       ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
+       ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
                                        &filter_idx, NULL);
        if (ret < 0) {
                PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
@@ -8459,9 +8472,13 @@ i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 
        switch (udp_tunnel->prot_type) {
        case RTE_TUNNEL_TYPE_VXLAN:
-               ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
+               ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
+                                         I40E_AQC_TUNNEL_TYPE_VXLAN);
+               break;
+       case RTE_TUNNEL_TYPE_VXLAN_GPE:
+               ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
+                                         I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
                break;
-
        case RTE_TUNNEL_TYPE_GENEVE:
        case RTE_TUNNEL_TYPE_TEREDO:
                PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
@@ -8490,6 +8507,7 @@ i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 
        switch (udp_tunnel->prot_type) {
        case RTE_TUNNEL_TYPE_VXLAN:
+       case RTE_TUNNEL_TYPE_VXLAN_GPE:
                ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
                break;
        case RTE_TUNNEL_TYPE_GENEVE:
@@ -11891,16 +11909,17 @@ static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
        struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        bool is_sfp = false;
        i40e_status status;
-       uint8_t *data = info->data;
+       uint8_t *data;
        uint32_t value = 0;
        uint32_t i;
 
-       if (!info || !info->length || !data)
+       if (!info || !info->length || !info->data)
                return -EINVAL;
 
        if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
                is_sfp = true;
 
+       data = info->data;
        for (i = 0; i < info->length; i++) {
                u32 offset = i + info->offset;
                u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
@@ -12700,9 +12719,6 @@ i40e_config_rss_filter(struct i40e_pf *pf,
                return -EINVAL;
        }
 
-       if (rss_info->conf.queue_num)
-               return -EINVAL;
-
        /* If both VMDQ and RSS enabled, not all of PF queues are configured.
         * It's necessary to calculate the actual PF queues that are configured.
         */