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net/i40e: fix parsing QinQ packets type
[dpdk.git] / drivers / net / i40e / i40e_ethdev.c
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index b04c833..535380a 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,7 +202,7 @@
 /* Source MAC address */
 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 /* Outer (S-Tag) VLAN tag in the outer L2 header */
-#define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
+#define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 /* Single VLAN tag in the inner L2 header */
@@ -663,10 +663,11 @@ static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 
 static struct eth_driver rte_i40e_pmd = {
        .pci_drv = {
-               .name = "rte_i40e_pmd",
                .id_table = pci_id_i40e_map,
                .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
                        RTE_PCI_DRV_DETACHABLE,
+               .probe = rte_eth_dev_pci_probe,
+               .remove = rte_eth_dev_pci_remove,
        },
        .eth_dev_init = eth_i40e_dev_init,
        .eth_dev_uninit = eth_i40e_dev_uninit,
@@ -701,33 +702,9 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
        return 0;
 }
 
-/*
- * Driver initialization routine.
- * Invoked once at EAL init time.
- * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
- */
-static int
-rte_i40e_pmd_init(const char *name __rte_unused,
-                 const char *params __rte_unused)
-{
-       PMD_INIT_FUNC_TRACE();
-       rte_eth_driver_register(&rte_i40e_pmd);
-
-       return 0;
-}
-
-static struct rte_driver rte_i40e_driver = {
-       .type = PMD_PDEV,
-       .init = rte_i40e_pmd_init,
-};
-
-PMD_REGISTER_DRIVER(rte_i40e_driver, net_i40e);
+DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 
-/*
- * Initialize registers for flexible payload, which should be set by NVM.
- * This should be removed from code once it is fixed in NVM.
- */
 #ifndef I40E_GLQF_ORT
 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 #endif
@@ -735,8 +712,12 @@ DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 #endif
 
-static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
+static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 {
+       /*
+        * Initialize registers for flexible payload, which should be set by NVM.
+        * This should be removed from code once it is fixed in NVM.
+        */
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
@@ -747,10 +728,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
-
-       /* GLQF_PIT Registers */
        I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
        I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
+
+       /* Initialize registers for parsing packet type of QinQ */
+       I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
+       I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 }
 
 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
@@ -924,14 +907,19 @@ config_floating_veb(struct rte_eth_dev *dev)
        memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 
        if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
-               pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
-               config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
+               pf->floating_veb =
+                       is_floating_veb_supported(pci_dev->device.devargs);
+               config_vf_floating_veb(pci_dev->device.devargs,
+                                      pf->floating_veb,
                                       pf->floating_veb_list);
        } else {
                pf->floating_veb = false;
        }
 }
 
+#define I40E_L2_TAGS_S_TAG_SHIFT 1
+#define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
+
 static int
 eth_i40e_dev_init(struct rte_eth_dev *dev)
 {
@@ -1002,11 +990,12 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
        }
 
        /*
-        * To work around the NVM issue,initialize registers
-        * for flexible payload by software.
-        * It should be removed once issues are fixed in NVM.
+        * To work around the NVM issue, initialize registers
+        * for flexible payload and packet type of QinQ by
+        * software. It should be removed once issues are fixed
+        * in NVM.
         */
-       i40e_flex_payload_reg_init(hw);
+       i40e_GLQF_reg_init(hw);
 
        /* Initialize the input set for filters (hash and fd) to default value */
        i40e_filter_input_set_init(pf);
@@ -1120,6 +1109,13 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
        /* Disable double vlan by default */
        i40e_vsi_config_double_vlan(vsi, FALSE);
 
+       /* Disable S-TAG identification by default */
+       ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
+       if (ret & I40E_L2_TAGS_S_TAG_MASK) {
+               ret &= ~I40E_L2_TAGS_S_TAG_MASK;
+               I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
+       }
+
        if (!vsi->max_macaddrs)
                len = ETHER_ADDR_LEN;
        else
@@ -6154,9 +6150,20 @@ i40e_config_hena(uint64_t flags)
        if (flags & ETH_RSS_FRAG_IPV4)
                hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
        if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
        if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
@@ -6164,9 +6171,20 @@ i40e_config_hena(uint64_t flags)
        if (flags & ETH_RSS_FRAG_IPV6)
                hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
        if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
        if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
@@ -6189,8 +6207,18 @@ i40e_parse_hena(uint64_t flags)
                rss_hf |= ETH_RSS_FRAG_IPV4;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
                rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
+               rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
                rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
                rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
@@ -6199,8 +6227,18 @@ i40e_parse_hena(uint64_t flags)
                rss_hf |= ETH_RSS_FRAG_IPV6;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
                rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
+               rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
                rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
                rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
@@ -7064,6 +7102,26 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
                        I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
+                       I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
+                       I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
+                       I40E_INSET_FLEX_PAYLOAD,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
+                       I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
+                       I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
+                       I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7073,6 +7131,17 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
                        I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
+                       I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
+                       I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
+                       I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7106,6 +7175,26 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
                        I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
                        I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
+                       I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
+                       I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
+                       I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
+                       I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
+                       I40E_INSET_FLEX_PAYLOAD,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
+                       I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
+                       I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
+                       I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
+                       I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
+                       I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7115,6 +7204,17 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
                        I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
                        I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
+                       I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
+                       I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
+                       I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
+                       I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
+                       I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7154,11 +7254,30 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
@@ -7180,11 +7299,30 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
@@ -7237,9 +7375,22 @@ i40e_get_default_input_set(uint16_t pctype)
                [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
@@ -7251,9 +7402,22 @@ i40e_get_default_input_set(uint16_t pctype)
                [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
                        I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+                       I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+                       I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                        I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+                       I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                        I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
@@ -7568,7 +7732,16 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
                PMD_DRV_LOG(ERR, "invalid flow_type input.");
                return -EINVAL;
        }
+
+#ifdef X722_SUPPORT
+       /* get translated pctype value in fd pctype register */
+       pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
+               I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
+               conf->flow_type)));
+#else
        pctype = i40e_flowtype_to_pctype(conf->flow_type);
+#endif
+
        ret = i40e_parse_input_set(&input_set, pctype, conf->field,
                                   conf->inset_size);
        if (ret) {
@@ -7637,7 +7810,9 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
                PMD_DRV_LOG(ERR, "invalid flow_type input.");
                return -EINVAL;
        }
+
        pctype = i40e_flowtype_to_pctype(conf->flow_type);
+
        ret = i40e_parse_input_set(&input_set, pctype, conf->field,
                                   conf->inset_size);
        if (ret) {
@@ -8010,8 +8185,18 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
                [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
                [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
                        RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                        RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+                       RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                        RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
                [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
@@ -8019,8 +8204,18 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
                [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
                [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
                        RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                        RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+                       RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                        RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
                [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
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