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ethdev: add an argument to internal callback function
[dpdk.git] / drivers / net / i40e / i40e_ethdev.c
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index cfea11f..5af0e43 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,7 +202,7 @@
 /* Source MAC address */
 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 /* Outer (S-Tag) VLAN tag in the outer L2 header */
-#define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
+#define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 /* Single VLAN tag in the inner L2 header */
@@ -411,6 +411,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
                                void *arg);
 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
                                  struct rte_eth_dcb_info *dcb_info);
+static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 static void i40e_configure_registers(struct i40e_hw *hw);
 static void i40e_hw_init(struct rte_eth_dev *dev);
 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
@@ -474,7 +475,6 @@ static const struct rte_pci_id pci_id_i40e_map[] = {
        { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
        { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
        { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
-       { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
        { .vendor_id = 0, /* sentinel */ },
 };
 
@@ -702,13 +702,9 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
        return 0;
 }
 
-DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
-DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
+RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
+RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 
-/*
- * Initialize registers for flexible payload, which should be set by NVM.
- * This should be removed from code once it is fixed in NVM.
- */
 #ifndef I40E_GLQF_ORT
 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 #endif
@@ -716,8 +712,12 @@ DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 #endif
 
-static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
+static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 {
+       /*
+        * Initialize registers for flexible payload, which should be set by NVM.
+        * This should be removed from code once it is fixed in NVM.
+        */
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
@@ -728,10 +728,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
        I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
-
-       /* GLQF_PIT Registers */
        I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
        I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
+
+       /* Initialize registers for parsing packet type of QinQ */
+       I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
+       I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 }
 
 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
@@ -915,6 +917,9 @@ config_floating_veb(struct rte_eth_dev *dev)
        }
 }
 
+#define I40E_L2_TAGS_S_TAG_SHIFT 1
+#define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
+
 static int
 eth_i40e_dev_init(struct rte_eth_dev *dev)
 {
@@ -985,11 +990,12 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
        }
 
        /*
-        * To work around the NVM issue,initialize registers
-        * for flexible payload by software.
-        * It should be removed once issues are fixed in NVM.
+        * To work around the NVM issue, initialize registers
+        * for flexible payload and packet type of QinQ by
+        * software. It should be removed once issues are fixed
+        * in NVM.
         */
-       i40e_flex_payload_reg_init(hw);
+       i40e_GLQF_reg_init(hw);
 
        /* Initialize the input set for filters (hash and fd) to default value */
        i40e_filter_input_set_init(pf);
@@ -1012,7 +1018,11 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
        config_floating_veb(dev);
        /* Clear PXE mode */
        i40e_clear_pxe_mode(hw);
-
+       ret = i40e_dev_sync_phy_type(hw);
+       if (ret) {
+               PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
+               goto err_sync_phy_type;
+       }
        /*
         * On X710, performance number is far from the expectation on recent
         * firmware versions. The fix for this issue may not be integrated in
@@ -1103,6 +1113,13 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
        /* Disable double vlan by default */
        i40e_vsi_config_double_vlan(vsi, FALSE);
 
+       /* Disable S-TAG identification by default */
+       ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
+       if (ret & I40E_L2_TAGS_S_TAG_MASK) {
+               ret &= ~I40E_L2_TAGS_S_TAG_MASK;
+               I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
+       }
+
        if (!vsi->max_macaddrs)
                len = ETHER_ADDR_LEN;
        else
@@ -1168,6 +1185,7 @@ err_msix_pool_init:
 err_qp_pool_init:
 err_parameter_init:
 err_get_capabilities:
+err_sync_phy_type:
        (void)i40e_shutdown_adminq(hw);
 
        return ret;
@@ -1551,6 +1569,8 @@ i40e_parse_link_speeds(uint16_t link_speeds)
 
        if (link_speeds & ETH_LINK_SPEED_40G)
                link_speed |= I40E_LINK_SPEED_40GB;
+       if (link_speeds & ETH_LINK_SPEED_25G)
+               link_speed |= I40E_LINK_SPEED_25GB;
        if (link_speeds & ETH_LINK_SPEED_20G)
                link_speed |= I40E_LINK_SPEED_20GB;
        if (link_speeds & ETH_LINK_SPEED_10G)
@@ -1576,6 +1596,7 @@ i40e_phy_conf_link(struct i40e_hw *hw,
                        I40E_AQ_PHY_FLAG_PAUSE_RX |
                        I40E_AQ_PHY_FLAG_LOW_POWER;
        const uint8_t advt = I40E_LINK_SPEED_40GB |
+                       I40E_LINK_SPEED_25GB |
                        I40E_LINK_SPEED_10GB |
                        I40E_LINK_SPEED_1GB |
                        I40E_LINK_SPEED_100MB;
@@ -1628,13 +1649,14 @@ i40e_apply_link_speed(struct rte_eth_dev *dev)
        struct rte_eth_conf *conf = &dev->data->dev_conf;
 
        speed = i40e_parse_link_speeds(conf->link_speeds);
-       abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+       if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+               abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
        if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
                abilities |= I40E_AQ_PHY_AN_ENABLED;
        abilities |= I40E_AQ_PHY_LINK_ENABLED;
 
        /* Skip changing speed on 40G interfaces, FW does not support */
-       if (i40e_is_40G_device(hw->device_id)) {
+       if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
                speed =  I40E_LINK_SPEED_UNKNOWN;
                abilities |= I40E_AQ_PHY_AN_ENABLED;
        }
@@ -1730,7 +1752,8 @@ i40e_dev_start(struct rte_eth_dev *dev)
        /* Apply link configure */
        if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
                                ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
-                               ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
+                               ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
+                               ETH_LINK_SPEED_40G)) {
                PMD_DRV_LOG(ERR, "Invalid link setting");
                goto err_up;
        }
@@ -1950,9 +1973,11 @@ static int
 i40e_dev_set_link_down(struct rte_eth_dev *dev)
 {
        uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
-       uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+       uint8_t abilities = 0;
        struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 
+       if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+               abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
        return i40e_phy_conf_link(hw, abilities, speed);
 }
 
@@ -2010,6 +2035,9 @@ i40e_dev_link_update(struct rte_eth_dev *dev,
        case I40E_LINK_SPEED_20GB:
                link.link_speed = ETH_SPEED_NUM_20G;
                break;
+       case I40E_LINK_SPEED_25GB:
+               link.link_speed = ETH_SPEED_NUM_25G;
+               break;
        case I40E_LINK_SPEED_40GB:
                link.link_speed = ETH_SPEED_NUM_40G;
                break;
@@ -2559,7 +2587,11 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
                DEV_TX_OFFLOAD_TCP_CKSUM |
                DEV_TX_OFFLOAD_SCTP_CKSUM |
                DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
-               DEV_TX_OFFLOAD_TCP_TSO;
+               DEV_TX_OFFLOAD_TCP_TSO |
+               DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
+               DEV_TX_OFFLOAD_GRE_TNL_TSO |
+               DEV_TX_OFFLOAD_IPIP_TNL_TSO |
+               DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
        dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
                                                sizeof(uint32_t);
        dev_info->reta_size = pf->hash_lut_size;
@@ -2609,9 +2641,12 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
                dev_info->max_tx_queues += dev_info->vmdq_queue_num;
        }
 
-       if (i40e_is_40G_device(hw->device_id))
+       if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
                /* For XL710 */
                dev_info->speed_capa = ETH_LINK_SPEED_40G;
+       else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
+               /* For XXV710 */
+               dev_info->speed_capa = ETH_LINK_SPEED_25G;
        else
                /* For X710 */
                dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
@@ -2857,7 +2892,7 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
        if (err < 0)
                return -ENOSYS;
 
-       if (i40e_is_40G_device(hw->device_id)) {
+       if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
                /* Configure flow control refresh threshold,
                 * the value for stat_tx_pause_refresh_timer[8]
                 * is used for global pause operation.
@@ -4080,11 +4115,13 @@ i40e_vsi_release(struct i40e_vsi *vsi)
        void *temp;
        int ret;
        struct i40e_mac_filter *f;
-       uint16_t user_param = vsi->user_param;
+       uint16_t user_param;
 
        if (!vsi)
                return I40E_SUCCESS;
 
+       user_param = vsi->user_param;
+
        pf = I40E_VSI_TO_PF(vsi);
        hw = I40E_VSI_TO_HW(vsi);
 
@@ -5479,7 +5516,7 @@ i40e_dev_interrupt_delayed_handler(void *param)
 
        /* handle the link up interrupt in an alarm callback */
        i40e_dev_link_update(dev, 0);
-       _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
+       _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 
        i40e_pf_enable_irq0(hw);
        rte_intr_enable(&(dev->pci_dev->intr_handle));
@@ -5563,7 +5600,7 @@ i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
                        return;
                else
                        _rte_eth_dev_callback_process(dev,
-                               RTE_ETH_EVENT_INTR_LSC);
+                               RTE_ETH_EVENT_INTR_LSC, NULL);
        }
 
 done:
@@ -6137,9 +6174,20 @@ i40e_config_hena(uint64_t flags)
        if (flags & ETH_RSS_FRAG_IPV4)
                hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
        if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
        if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
@@ -6147,9 +6195,20 @@ i40e_config_hena(uint64_t flags)
        if (flags & ETH_RSS_FRAG_IPV6)
                hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
        if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
+#ifdef X722_SUPPORT
+               hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
+                       (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
+#else
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
+#endif
        if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
                hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
        if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
@@ -6172,8 +6231,18 @@ i40e_parse_hena(uint64_t flags)
                rss_hf |= ETH_RSS_FRAG_IPV4;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
                rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
+               rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
                rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
                rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
@@ -6182,8 +6251,18 @@ i40e_parse_hena(uint64_t flags)
                rss_hf |= ETH_RSS_FRAG_IPV6;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
                rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
+               rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
                rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+#ifdef X722_SUPPORT
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+       if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
+               rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+#endif
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
                rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
        if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
@@ -7047,6 +7126,26 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
                        I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
+                       I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
+                       I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
+                       I40E_INSET_FLEX_PAYLOAD,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
+                       I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
+                       I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
+                       I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7056,6 +7155,17 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
                        I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
+                       I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
+                       I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
+                       I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7089,6 +7199,26 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
                        I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
                        I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
+                       I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
+                       I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
+                       I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
+                       I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
+                       I40E_INSET_FLEX_PAYLOAD,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
+                       I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
+                       I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
+                       I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
+                       I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
+                       I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7098,6 +7228,17 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                        I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
                        I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
                        I40E_INSET_FLEX_PAYLOAD,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+                       I40E_INSET_DMAC | I40E_INSET_SMAC |
+                       I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+                       I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
+                       I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
+                       I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
+                       I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
+                       I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
+                       I40E_INSET_FLEX_PAYLOAD,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                        I40E_INSET_DMAC | I40E_INSET_SMAC |
                        I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
@@ -7137,11 +7278,30 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
@@ -7163,11 +7323,30 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+               I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
@@ -7220,9 +7399,22 @@ i40e_get_default_input_set(uint16_t pctype)
                [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+                       I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                        I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
@@ -7234,9 +7426,22 @@ i40e_get_default_input_set(uint16_t pctype)
                [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
                        I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+                       I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+                       I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                        I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+                       I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+                       I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                        I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
                        I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
@@ -7551,7 +7756,16 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
                PMD_DRV_LOG(ERR, "invalid flow_type input.");
                return -EINVAL;
        }
+
+#ifdef X722_SUPPORT
+       /* get translated pctype value in fd pctype register */
+       pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
+               I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
+               conf->flow_type)));
+#else
        pctype = i40e_flowtype_to_pctype(conf->flow_type);
+#endif
+
        ret = i40e_parse_input_set(&input_set, pctype, conf->field,
                                   conf->inset_size);
        if (ret) {
@@ -7620,7 +7834,9 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
                PMD_DRV_LOG(ERR, "invalid flow_type input.");
                return -EINVAL;
        }
+
        pctype = i40e_flowtype_to_pctype(conf->flow_type);
+
        ret = i40e_parse_input_set(&input_set, pctype, conf->field,
                                   conf->inset_size);
        if (ret) {
@@ -7993,8 +8209,18 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
                [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
                [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
                        RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
                        RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
+                       RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                        RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
                [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
@@ -8002,8 +8228,18 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
                [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
                [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
                        RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
+               [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
+                       RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
                        RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
+#ifdef X722_SUPPORT
+               [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
+                       RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
+#endif
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                        RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
                [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
@@ -8039,6 +8275,23 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
 
+static int
+i40e_dev_sync_phy_type(struct i40e_hw *hw)
+{
+       enum i40e_status_code status;
+       struct i40e_aq_get_phy_abilities_resp phy_ab;
+       int ret = -ENOTSUP;
+
+       status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
+                                             NULL);
+
+       if (status)
+               return ret;
+
+       return 0;
+}
+
+
 static void
 i40e_configure_registers(struct i40e_hw *hw)
 {
@@ -8056,7 +8309,8 @@ i40e_configure_registers(struct i40e_hw *hw)
 
        for (i = 0; i < RTE_DIM(reg_table); i++) {
                if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
-                       if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
+                       if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
+                           I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
                                reg_table[i].val =
                                        I40E_GL_SWR_PM_UP_THR_SF_VALUE;
                        else /* For X710 */
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