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i40e: allow filtering on more IP header fields
[dpdk.git] / drivers / net / i40e / i40e_ethdev.c
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index e5404f7..6034d58 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -210,6 +210,8 @@
 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 /* IPv4 Protocol */
 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
+/* IPv4 Time to Live */
+#define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 /* Source IPv6 address */
 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 /* Destination IPv6 address */
@@ -218,6 +220,8 @@
 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 /* IPv6 Next Header */
 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
+/* IPv6 Hop Limit */
+#define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 /* Source L4 port */
 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 /* Destination L4 port */
@@ -261,10 +265,12 @@
 #define I40E_TRANSLATE_INSET 0
 #define I40E_TRANSLATE_REG   1
 
-#define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
-#define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
-#define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
-#define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
+#define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
+#define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
+#define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
+#define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
+#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
+#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 
 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
@@ -6761,30 +6767,47 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
         */
        static const uint64_t valid_fdir_inset_table[] = {
                [I40E_FILTER_PCTYPE_FRAG_IPV4] =
-               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+               I40E_INSET_IPV4_TTL,
                [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
                [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
-               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
                [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
                I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
                I40E_INSET_SCTP_VT,
                [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
-               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
+               I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
+               I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+               I40E_INSET_IPV4_TTL,
                [I40E_FILTER_PCTYPE_FRAG_IPV6] =
-               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
+               I40E_INSET_IPV6_HOP_LIMIT,
                [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
-               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
                [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
-               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
+               I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
                [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
                I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
                I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
                I40E_INSET_SCTP_VT,
                [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
-               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
+               I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
+               I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
+               I40E_INSET_IPV6_HOP_LIMIT,
                [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
                I40E_INSET_LAST_ETHER_TYPE,
        };
@@ -6884,11 +6907,14 @@ i40e_parse_input_set(uint64_t *inset,
                {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
                {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
                {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
+               {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
                {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
                {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
                {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
                {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
                        I40E_INSET_IPV6_NEXT_HDR},
+               {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
+                       I40E_INSET_IPV6_HOP_LIMIT},
                {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
                {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
                {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
@@ -6975,10 +7001,12 @@ i40e_translate_input_set_reg(uint64_t input)
                {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
                {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
                {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
+               {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
                {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
                {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
                {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
                {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
+               {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
                {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
                {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
                {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
@@ -7018,23 +7046,38 @@ static int
 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
 {
        uint8_t i, idx = 0;
+       uint64_t inset_need_mask = inset;
 
        static const struct {
                uint64_t inset;
                uint32_t mask;
        } inset_mask_map[] = {
                {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
+               {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
                {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
+               {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
                {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
+               {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
                {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
+               {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
        };
 
        if (!inset || !mask || !nb_elem)
                return 0;
 
-
        for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
-               if ((inset & inset_mask_map[i].inset) == inset_mask_map[i].inset) {
+               /* Clear the inset bit, if no MASK is required,
+                * for example proto + ttl
+                */
+               if ((inset & inset_mask_map[i].inset) ==
+                    inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
+                       inset_need_mask &= ~inset_mask_map[i].inset;
+               if (!inset_need_mask)
+                       return 0;
+       }
+       for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
+               if ((inset_need_mask & inset_mask_map[i].inset) ==
+                   inset_mask_map[i].inset) {
                        if (idx >= nb_elem) {
                                PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
                                return -EINVAL;
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