#include <rte_tailq.h>
#include <rte_hash_crc.h>
#include <rte_bitmap.h>
+#include <rte_os_shim.h>
#include "i40e_logs.h"
#include "base/i40e_prototype.h"
static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
struct rte_eth_udp_tunnel *udp_tunnel);
static void i40e_filter_input_set_init(struct i40e_pf *pf);
-static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
- enum rte_filter_type filter_type,
- enum rte_filter_op filter_op,
- void *arg);
+static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
+ const struct rte_flow_ops **ops);
static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
struct rte_eth_dcb_info *dcb_info);
static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
.rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
.udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
.udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
- .filter_ctrl = i40e_dev_filter_ctrl,
+ .flow_ops_get = i40e_dev_flow_ops_get,
.rxq_info_get = i40e_rxq_info_get,
.txq_info_get = i40e_txq_info_get,
.rx_burst_mode_get = i40e_rx_burst_mode_get,
uint32_t reg_val)
{
uint32_t ori_reg_val;
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
i40e_write_rx_ctl(hw, reg_addr, reg_val);
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
idx = strtoul(floating_veb_value, &end, 10);
if (errno || end == NULL)
return -1;
+ if (idx < 0)
+ return -1;
while (isblank(*end))
end++;
if (*end == '-') {
char fdir_hash_name[RTE_HASH_NAMESIZE];
uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
uint32_t best = hw->func_caps.fd_filters_best_effort;
+ enum i40e_filter_pctype pctype;
struct rte_bitmap *bmp = NULL;
uint32_t bmp_size;
void *mem = NULL;
goto err_fdir_filter_array_alloc;
}
+ for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+ pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
+ pf->fdir.flow_count[pctype] = 0;
+
fdir_info->fdir_space_size = alloc + best;
fdir_info->fdir_actual_cnt = 0;
fdir_info->fdir_guarantee_total_space = alloc;
struct i40e_asq_cmd_details *cmd_details)
{
uint64_t ori_reg_val;
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
int ret;
ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
reg_addr);
return -EIO;
}
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
- pf->adapter->eth_dev = dev;
pf->dev_data = dev->data;
hw->back = I40E_PF_TO_ADAPTER(pf);
void
i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
int
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
void
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
void
i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
- I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
+ I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
+ I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
phy_conf.eee_capability = phy_ab.eee_capability;
phy_conf.eeer = phy_ab.eeer_val;
((hw->nvm.version >> 4) & 0xff),
(hw->nvm.version & 0xf), hw->nvm.eetrack,
ver, build, patch);
+ if (ret < 0)
+ return -EINVAL;
ret += 1; /* add the size of '\0' */
- if (fw_size < (u32)ret)
+ if (fw_size < (size_t)ret)
return ret;
else
return 0;
u64 size,
u32 alignment)
{
+ static uint64_t i40e_dma_memzone_id;
const struct rte_memzone *mz = NULL;
char z_name[RTE_MEMZONE_NAMESIZE];
if (!mem)
return I40E_ERR_PARAM;
- snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
+ snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
+ __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
if (!mz)
break;
}
if (ret == I40E_SUCCESS)
- i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
- ->eth_dev);
+ i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
return ret;
}
}
}
if (ret == I40E_SUCCESS)
- i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
- ->eth_dev);
+ i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
return ret;
}
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
enum i40e_status_code status = I40E_SUCCESS;
if (pf->support_multi_driver) {
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = i40e_read_rx_ctl(hw, addr);
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
if (reg != val) {
i40e_write_rx_ctl(hw, addr, val);
PMD_DRV_LOG(WARNING,
}
static int
-i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
- enum rte_filter_type filter_type,
- enum rte_filter_op filter_op,
- void *arg)
+i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
+ const struct rte_flow_ops **ops)
{
- int ret = 0;
-
if (dev == NULL)
return -EINVAL;
- switch (filter_type) {
- case RTE_ETH_FILTER_GENERIC:
- if (filter_op != RTE_ETH_FILTER_GET)
- return -EINVAL;
- *(const void **)arg = &i40e_flow_ops;
- break;
- default:
- PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
- filter_type);
- ret = -EINVAL;
- break;
- }
-
- return ret;
+ *ops = &i40e_flow_ops;
+ return 0;
}
/*
uint32_t value = 0;
uint32_t i;
- if (!info || !info->length || !info->data)
- return -EINVAL;
-
if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
is_sfp = true;
struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
- struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
if (pf->support_multi_driver) {
PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
return ret;
}
-RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
-RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
-#ifdef RTE_LIBRTE_I40E_DEBUG_RX
-RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
-#endif
-#ifdef RTE_LIBRTE_I40E_DEBUG_TX
-RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
+RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
+RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
+#ifdef RTE_ETHDEV_DEBUG_RX
+RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
#endif
-#ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
-RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
+#ifdef RTE_ETHDEV_DEBUG_TX
+RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
#endif
RTE_PMD_REGISTER_PARAM_STRING(net_i40e,