(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
(1UL << RTE_ETH_FLOW_L2_PAYLOAD))
-#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
-#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
-#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
-#define I40E_PRTTSYN_TSYNENA 0x80000000
-#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
+/* Additional timesync values. */
+#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
+#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
+#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
+#define I40E_PRTTSYN_TSYNENA 0x80000000
+#define I40E_PRTTSYN_TSYNTYPE 0x0e000000
+#define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
#define I40E_MAX_PERCENT 100
#define I40E_DEFAULT_DCB_APP_NUM 1
#define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
#define I40E_INSET_FLEX_PAYLOAD \
(I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
- I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
+ I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
/* Source MAC address */
#define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
/* VLAN tag in the outer L2 header */
-#define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000000800000ULL
+#define I40E_REG_INSET_L2_OUTER_VLAN 0x0080000000000000ULL
/* VLAN tag in the inner L2 header */
-#define I40E_REG_INSET_L2_INNER_VLAN 0x0000000001000000ULL
+#define I40E_REG_INSET_L2_INNER_VLAN 0x0100000000000000ULL
/* Source IPv4 address */
#define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
/* Destination IPv4 address */
#define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
#define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
+#define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
+#define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
+#define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
+ I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
+
+/* PCI offset for querying capability */
+#define PCI_DEV_CAP_REG 0xA4
+/* PCI offset for enabling/disabling Extended Tag */
+#define PCI_DEV_CTRL_REG 0xA8
+/* Bit mask of Extended Tag capability */
+#define PCI_DEV_CAP_EXT_TAG_MASK 0x20
+/* Bit shift of Extended Tag enable/disable */
+#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
+/* Bit mask of Extended Tag enable/disable */
+#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
+
static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
static int i40e_dev_configure(struct rte_eth_dev *dev);
static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
uint16_t vlan_id,
int on);
-static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
+static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
+ enum rte_vlan_type vlan_type,
+ uint16_t tpid);
static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
uint16_t queue,
struct rte_eth_rss_conf *rss_conf);
static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
struct rte_eth_rss_conf *rss_conf);
-static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
- struct rte_eth_udp_tunnel *udp_tunnel);
-static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
- struct rte_eth_udp_tunnel *udp_tunnel);
+static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
+ struct rte_eth_udp_tunnel *udp_tunnel);
+static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
+ struct rte_eth_udp_tunnel *udp_tunnel);
static int i40e_ethertype_filter_set(struct i40e_pf *pf,
struct rte_eth_ethertype_filter *filter,
bool add);
static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
struct rte_eth_dcb_info *dcb_info);
static void i40e_configure_registers(struct i40e_hw *hw);
-static void i40e_hw_init(struct i40e_hw *hw);
+static void i40e_hw_init(struct rte_eth_dev *dev);
static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
struct rte_eth_mirror_conf *mirror_conf,
static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
struct timespec *timestamp);
static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
+
+static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+
+static int i40e_timesync_read_time(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+static int i40e_timesync_write_time(struct rte_eth_dev *dev,
+ const struct timespec *timestamp);
+
static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
uint16_t queue_id);
static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
uint16_t queue_id);
+
static const struct rte_pci_id pci_id_i40e_map[] = {
#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "rte_pci_dev_ids.h"
.reta_query = i40e_dev_rss_reta_query,
.rss_hash_update = i40e_dev_rss_hash_update,
.rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
- .udp_tunnel_add = i40e_dev_udp_tunnel_add,
- .udp_tunnel_del = i40e_dev_udp_tunnel_del,
+ .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
+ .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
.filter_ctrl = i40e_dev_filter_ctrl,
.rxq_info_get = i40e_rxq_info_get,
.txq_info_get = i40e_txq_info_get,
.timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
.get_dcb_info = i40e_dev_get_dcb_info,
+ .timesync_adjust_time = i40e_timesync_adjust_time,
+ .timesync_read_time = i40e_timesync_read_time,
+ .timesync_write_time = i40e_timesync_write_time,
};
/* store statistics names and its offset in stats structure */
{"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
};
+#define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
+ sizeof(rte_i40e_stats_strings[0]))
+
static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
{"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
tx_dropped_link_down)},
rx_lpi_count)},
};
-/* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
-#define I40E_NB_HW_PORT_Q_STATS (8 * 5)
-
-#define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
- sizeof(rte_i40e_stats_strings[0]))
#define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
sizeof(rte_i40e_hw_port_strings[0]))
-#define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
- I40E_NB_HW_PORT_Q_STATS)
+
+static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
+ {"xon_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xon_rx)},
+ {"xoff_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xoff_rx)},
+};
+
+#define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
+ sizeof(rte_i40e_rxq_prio_strings[0]))
+
+static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
+ {"xon_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xon_tx)},
+ {"xoff_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xoff_tx)},
+ {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
+ priority_xon_2_xoff)},
+};
+
+#define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
+ sizeof(rte_i40e_txq_prio_strings[0]))
static struct eth_driver rte_i40e_pmd = {
.pci_drv = {
i40e_clear_hw(hw);
/* Initialize the hardware */
- i40e_hw_init(hw);
+ i40e_hw_init(dev);
/* Reset here to make sure all is clean for each PF */
ret = i40e_pf_reset(hw);
hw->fc.requested_mode = I40E_FC_NONE;
i40e_set_fc(hw, &aq_fail, TRUE);
+ /* Set the global registers with default ether type value */
+ ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
+ if (ret != I40E_SUCCESS) {
+ PMD_INIT_LOG(ERR, "Failed to set the default outer "
+ "VLAN ether type");
+ goto err_setup_pf_switch;
+ }
+ ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
+ if (ret != I40E_SUCCESS) {
+ PMD_INIT_LOG(ERR, "Failed to set the default outer "
+ "VLAN ether type");
+ goto err_setup_pf_switch;
+ }
+
/* PF setup, which includes VSI setup */
ret = i40e_pf_setup(pf);
if (ret) {
*/
i40e_add_tx_flow_control_drop_filter(pf);
+ /* Set the max frame size to 0x2600 by default,
+ * in case other drivers changed the default value.
+ */
+ i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
+
/* initialize mirror rule list */
TAILQ_INIT(&pf->mirror_list);
}
static int
-i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
-{
- enum i40e_status_code status;
- struct i40e_aq_get_phy_abilities_resp phy_ab;
- struct i40e_aq_set_phy_config phy_conf;
- const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
- I40E_AQ_PHY_FLAG_PAUSE_RX |
- I40E_AQ_PHY_FLAG_LOW_POWER;
- const uint8_t advt = I40E_LINK_SPEED_40GB |
- I40E_LINK_SPEED_10GB |
- I40E_LINK_SPEED_1GB |
- I40E_LINK_SPEED_100MB;
- int ret = -ENOTSUP;
-
- /* Skip it on 40G interfaces, as a workaround for the link issue */
- if (i40e_is_40G_device(hw->device_id))
- return I40E_SUCCESS;
-
- status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
- NULL);
- if (status)
- return ret;
-
- memset(&phy_conf, 0, sizeof(phy_conf));
-
- /* bits 0-2 use the values from get_phy_abilities_resp */
- abilities &= ~mask;
- abilities |= phy_ab.abilities & mask;
-
- /* update ablities and speed */
- if (abilities & I40E_AQ_PHY_AN_ENABLED)
- phy_conf.link_speed = advt;
- else
- phy_conf.link_speed = force_speed;
-
- phy_conf.abilities = abilities;
-
- /* use get_phy_abilities_resp value for the rest */
- phy_conf.phy_type = phy_ab.phy_type;
- phy_conf.eee_capability = phy_ab.eee_capability;
- phy_conf.eeer = phy_ab.eeer_val;
- phy_conf.low_power_ctrl = phy_ab.d3_lpan;
-
- PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
- phy_ab.abilities, phy_ab.link_speed);
- PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
- phy_conf.abilities, phy_conf.link_speed);
-
- status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
- if (status)
- return ret;
-
+i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
+ __rte_unused uint8_t abilities,
+ __rte_unused uint8_t force_speed)
+{
+ /* Skip any phy config on both 10G and 40G interfaces, as a workaround
+ * for the link control limitation of that all link control should be
+ * handled by firmware. It should follow up if link control will be
+ * opened to software driver in future firmware versions.
+ */
return I40E_SUCCESS;
}
unsigned int i;
struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
+
/* Get statistics of struct i40e_eth_stats */
i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
I40E_GLPRT_GORCL(hw->port),
I40E_GLPRT_BPRCL(hw->port),
pf->offset_loaded, &os->eth.rx_broadcast,
&ns->eth.rx_broadcast);
+ /* Workaround: CRC size should not be included in byte statistics,
+ * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
+ */
+ ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
+ ns->eth.rx_broadcast) * ETHER_CRC_LEN;
+
i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
pf->offset_loaded, &os->eth.rx_discards,
&ns->eth.rx_discards);
I40E_GLPRT_BPTCL(hw->port),
pf->offset_loaded, &os->eth.tx_broadcast,
&ns->eth.tx_broadcast);
+ ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
+ ns->eth.tx_broadcast) * ETHER_CRC_LEN;
/* GLPRT_TEPC not supported */
/* additional port specific stats */
stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
pf->main_vsi->eth_stats.tx_multicast +
pf->main_vsi->eth_stats.tx_broadcast;
- stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
- stats->obytes = pf->main_vsi->eth_stats.tx_bytes;
+ stats->ibytes = ns->eth.rx_bytes;
+ stats->obytes = ns->eth.tx_bytes;
stats->oerrors = ns->eth.tx_errors +
pf->main_vsi->eth_stats.tx_errors;
stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
- stats->fdirmatch = ns->fd_sb_match;
/* Rx Errors */
- stats->ibadcrc = ns->crc_errors;
- stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
- ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
stats->imissed = ns->eth.rx_discards +
pf->main_vsi->eth_stats.rx_discards;
- stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
+ stats->ierrors = ns->crc_errors +
+ ns->rx_length_errors + ns->rx_undersize +
+ ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
+ stats->imissed;
PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
i40e_read_stats_registers(pf, hw);
}
+static uint32_t
+i40e_xstats_calc_num(void)
+{
+ return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
+ (I40E_NB_RXQ_PRIO_XSTATS * 8) +
+ (I40E_NB_TXQ_PRIO_XSTATS * 8);
+}
+
static int
i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
unsigned n)
{
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- unsigned i, count = 0;
+ unsigned i, count, prio;
struct i40e_hw_port_stats *hw_stats = &pf->stats;
- if (n < I40E_NB_XSTATS)
- return I40E_NB_XSTATS;
+ count = i40e_xstats_calc_num();
+ if (n < count)
+ return count;
i40e_read_stats_registers(pf, hw);
- /* Reset */
if (xstats == NULL)
return 0;
+ count = 0;
+
/* Get stats from i40e_eth_stats struct */
for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
snprintf(xstats[count].name, sizeof(xstats[count].name),
count++;
}
- /* Get per-queue stats from i40e_hw_port struct */
- for (i = 0; i < 8; i++) {
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "rx_q%u_xon_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xon_rx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "rx_q%u_xoff_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xoff_rx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "tx_q%u_xon_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xon_tx[i]));
- count++;
-
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "tx_q%u_xoff_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xoff_tx[i]));
- count++;
+ for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
+ for (prio = 0; prio < 8; prio++) {
+ snprintf(xstats[count].name,
+ sizeof(xstats[count].name),
+ "rx_priority%u_%s", prio,
+ rte_i40e_rxq_prio_strings[i].name);
+ xstats[count].value =
+ *(uint64_t *)(((char *)hw_stats) +
+ rte_i40e_rxq_prio_strings[i].offset +
+ (sizeof(uint64_t) * prio));
+ count++;
+ }
+ }
- snprintf(xstats[count].name, sizeof(xstats[count].name),
- "xx_q%u_xon_to_xoff_priority_packets", i);
- xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
- offsetof(struct i40e_hw_port_stats,
- priority_xon_2_xoff[i]));
- count++;
+ for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
+ for (prio = 0; prio < 8; prio++) {
+ snprintf(xstats[count].name,
+ sizeof(xstats[count].name),
+ "tx_priority%u_%s", prio,
+ rte_i40e_txq_prio_strings[i].name);
+ xstats[count].value =
+ *(uint64_t *)(((char *)hw_stats) +
+ rte_i40e_txq_prio_strings[i].offset +
+ (sizeof(uint64_t) * prio));
+ count++;
+ }
}
- return I40E_NB_XSTATS;
+ return count;
}
static int
return i40e_vsi_delete_vlan(vsi, vlan_id);
}
-static void
-i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
- __rte_unused uint16_t tpid)
+static int
+i40e_vlan_tpid_set(struct rte_eth_dev *dev,
+ enum rte_vlan_type vlan_type,
+ uint16_t tpid)
{
- PMD_INIT_FUNC_TRACE();
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t reg_r = 0, reg_w = 0;
+ uint16_t reg_id = 0;
+ int ret = 0;
+
+ switch (vlan_type) {
+ case ETH_VLAN_TYPE_OUTER:
+ reg_id = 2;
+ break;
+ case ETH_VLAN_TYPE_INNER:
+ reg_id = 3;
+ break;
+ default:
+ ret = -EINVAL;
+ PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
+ return ret;
+ }
+ ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
+ ®_r, NULL);
+ if (ret != I40E_SUCCESS) {
+ PMD_DRV_LOG(ERR, "Fail to debug read from "
+ "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
+ ret = -EIO;
+ return ret;
+ }
+ PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
+ "0x%08"PRIx64"", reg_id, reg_r);
+
+ reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
+ reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
+ if (reg_r == reg_w) {
+ ret = 0;
+ PMD_DRV_LOG(DEBUG, "No need to write");
+ return ret;
+ }
+
+ ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
+ reg_w, NULL);
+ if (ret != I40E_SUCCESS) {
+ ret = -EIO;
+ PMD_DRV_LOG(ERR, "Fail to debug write to "
+ "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
+ return ret;
+ }
+ PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
+ "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
+
+ return ret;
}
static void
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_vsi *vsi = pf->main_vsi;
+ if (mask & ETH_VLAN_FILTER_MASK) {
+ if (dev->data->dev_conf.rxmode.hw_vlan_filter)
+ i40e_vsi_config_vlan_filter(vsi, TRUE);
+ else
+ i40e_vsi_config_vlan_filter(vsi, FALSE);
+ }
+
if (mask & ETH_VLAN_STRIP_MASK) {
/* Enable or disable VLAN stripping */
if (dev->data->dev_conf.rxmode.hw_vlan_strip)
}
(void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
- mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+ if (dev->data->dev_conf.rxmode.hw_vlan_filter)
+ mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
+ else
+ mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
if (pool == 0)
vsi = pf->main_vsi;
return I40E_ERR_PARAM;
snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
-#ifdef RTE_LIBRTE_XEN_DOM0
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
alignment, RTE_PGSIZE_2M);
-#else
- mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
- alignment);
-#endif
if (!mz)
return I40E_ERR_NO_MEMORY;
mem->size = size;
mem->va = mz->addr;
-#ifdef RTE_LIBRTE_XEN_DOM0
mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
-#else
- mem->pa = mz->phys_addr;
-#endif
mem->zone = (const void *)mz;
PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
"%"PRIu64, mz->name, mem->pa);
pool->num_free -= valid_entry->len;
pool->num_alloc += valid_entry->len;
- return (valid_entry->base + pool->base);
+ return valid_entry->base + pool->base;
}
/**
return i40e_vsi_add_mac(vsi, &filter);
}
-static int
-i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
+#define I40E_3_BIT_MASK 0x7
+/*
+ * i40e_vsi_get_bw_config - Query VSI BW Information
+ * @vsi: the VSI to be queried
+ *
+ * Returns 0 on success, negative value on failure
+ */
+static enum i40e_status_code
+i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
{
struct i40e_aqc_query_vsi_bw_config_resp bw_config;
struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
struct i40e_hw *hw = &vsi->adapter->hw;
i40e_status ret;
int i;
+ uint32_t bw_max;
memset(&bw_config, 0, sizeof(bw_config));
ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
return ret;
}
- /* Not store the info yet, just print out */
- PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
- PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
+ /* store and print out BW info */
+ vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
+ vsi->bw_info.bw_max = bw_config.max_bw;
+ PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
+ PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
+ bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
+ (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
+ I40E_16_BIT_WIDTH);
for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
- PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
- ets_sla_config.share_credits[i]);
- PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
- rte_le_to_cpu_16(ets_sla_config.credits[i]));
- PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
- rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
- (i * 4));
+ vsi->bw_info.bw_ets_share_credits[i] =
+ ets_sla_config.share_credits[i];
+ vsi->bw_info.bw_ets_credits[i] =
+ rte_le_to_cpu_16(ets_sla_config.credits[i]);
+ /* 4 bits per TC, 4th bit is reserved */
+ vsi->bw_info.bw_ets_max[i] =
+ (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
+ I40E_3_BIT_MASK);
+ PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
+ vsi->bw_info.bw_ets_share_credits[i]);
+ PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
+ vsi->bw_info.bw_ets_credits[i]);
+ PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
+ vsi->bw_info.bw_ets_max[i]);
}
- return 0;
+ return I40E_SUCCESS;
}
/* Setup a VSI */
}
/* Get VSI BW information */
- i40e_vsi_dump_bw_config(vsi);
+ i40e_vsi_get_bw_config(vsi);
return vsi;
fail_msix_alloc:
i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
return NULL;
}
+/* Configure vlan filter on or off */
+int
+i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
+{
+ int i, num;
+ struct i40e_mac_filter *f;
+ struct i40e_mac_filter_info *mac_filter;
+ enum rte_mac_filter_type desired_filter;
+ int ret = I40E_SUCCESS;
+
+ if (on) {
+ /* Filter to match MAC and VLAN */
+ desired_filter = RTE_MACVLAN_PERFECT_MATCH;
+ } else {
+ /* Filter to match only MAC */
+ desired_filter = RTE_MAC_PERFECT_MATCH;
+ }
+
+ num = vsi->mac_num;
+
+ mac_filter = rte_zmalloc("mac_filter_info_data",
+ num * sizeof(*mac_filter), 0);
+ if (mac_filter == NULL) {
+ PMD_DRV_LOG(ERR, "failed to allocate memory");
+ return I40E_ERR_NO_MEMORY;
+ }
+
+ i = 0;
+
+ /* Remove all existing mac */
+ TAILQ_FOREACH(f, &vsi->mac_list, next) {
+ mac_filter[i] = f->mac_info;
+ ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
+ if (ret) {
+ PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
+ on ? "enable" : "disable");
+ goto DONE;
+ }
+ i++;
+ }
+
+ /* Override with new filter */
+ for (i = 0; i < num; i++) {
+ mac_filter[i].filter_type = desired_filter;
+ ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
+ if (ret) {
+ PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
+ on ? "enable" : "disable");
+ goto DONE;
+ }
+ }
+
+DONE:
+ rte_free(mac_filter);
+ return ret;
+}
+
/* Configure vlan stripping on or off */
int
i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
{
struct rte_eth_dev_data *data = dev->data;
int ret;
+ int mask = 0;
/* Apply vlan offload setting */
- i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
+ mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
+ i40e_vlan_offload_set(dev, mask);
/* Apply double-vlan setting, not implemented yet */
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
int ret = 0;
- if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
- sizeof(uint32_t)))
+ if (!key || key_len == 0) {
+ PMD_DRV_LOG(DEBUG, "No key to be configured");
+ return 0;
+ } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
+ sizeof(uint32_t)) {
+ PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
return -EINVAL;
+ }
if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
struct i40e_aqc_get_set_rss_key_data *key_dw =
case ETH_TUNNEL_FILTER_IMAC:
*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
break;
+ case ETH_TUNNEL_FILTER_OIP:
+ *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
+ break;
+ case ETH_TUNNEL_FILTER_IIP:
+ *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
+ break;
default:
PMD_DRV_LOG(ERR, "invalid tunnel filter type");
return -EINVAL;
uint8_t add)
{
uint16_t ip_type;
- uint8_t tun_type = 0;
+ uint8_t i, tun_type = 0;
+ /* internal varialbe to convert ipv6 byte order */
+ uint32_t convert_ipv6[4];
int val, ret = 0;
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
struct i40e_vsi *vsi = pf->main_vsi;
}
pfilter = cld_filter;
- (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
- sizeof(struct ether_addr));
- (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
- sizeof(struct ether_addr));
+ ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
+ ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
- pfilter->inner_vlan = tunnel_filter->inner_vlan;
+ pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
- (void)rte_memcpy(&pfilter->ipaddr.v4.data,
- &tunnel_filter->ip_addr,
+ rte_memcpy(&pfilter->ipaddr.v4.data,
+ &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
sizeof(pfilter->ipaddr.v4.data));
} else {
ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
- (void)rte_memcpy(&pfilter->ipaddr.v6.data,
- &tunnel_filter->ip_addr,
+ for (i = 0; i < 4; i++) {
+ convert_ipv6[i] =
+ rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
+ }
+ rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
sizeof(pfilter->ipaddr.v6.data));
}
case RTE_TUNNEL_TYPE_NVGRE:
tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
break;
+ case RTE_TUNNEL_TYPE_IP_IN_GRE:
+ tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
+ break;
default:
/* Other tunnel types is not supported. */
PMD_DRV_LOG(ERR, "tunnel type is not supported.");
return -EINVAL;
}
- pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
- (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
- pfilter->tenant_id = tunnel_filter->tenant_id;
- pfilter->queue_number = tunnel_filter->queue_id;
+ pfilter->flags |= rte_cpu_to_le_16(
+ I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
+ ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
+ pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
+ pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
if (add)
ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
/* Add UDP tunneling port */
static int
-i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
- struct rte_eth_udp_tunnel *udp_tunnel)
+i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
+ struct rte_eth_udp_tunnel *udp_tunnel)
{
int ret = 0;
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
/* Remove UDP tunneling port */
static int
-i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
- struct rte_eth_udp_tunnel *udp_tunnel)
+i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
+ struct rte_eth_udp_tunnel *udp_tunnel)
{
int ret = 0;
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
}
if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
- (is_zero_ether_addr(filter->outer_mac))) {
+ (is_zero_ether_addr(&filter->outer_mac))) {
PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
return -EINVAL;
}
if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
- (is_zero_ether_addr(filter->inner_mac))) {
+ (is_zero_ether_addr(&filter->inner_mac))) {
PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
return -EINVAL;
}
return ret;
}
+/*
+ * Check and enable Extended Tag.
+ * Enabling Extended Tag is important for 40G performance.
+ */
+static void
+i40e_enable_extended_tag(struct rte_eth_dev *dev)
+{
+ uint32_t buf = 0;
+ int ret;
+
+ ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
+ PCI_DEV_CAP_REG);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+ PCI_DEV_CAP_REG);
+ return;
+ }
+ if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
+ PMD_DRV_LOG(ERR, "Does not support Extended Tag");
+ return;
+ }
+
+ buf = 0;
+ ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
+ PCI_DEV_CTRL_REG);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+ PCI_DEV_CTRL_REG);
+ return;
+ }
+ if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
+ PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
+ return;
+ }
+ buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
+ ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
+ PCI_DEV_CTRL_REG);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
+ PCI_DEV_CTRL_REG);
+ return;
+ }
+}
+
/*
* As some registers wouldn't be reset unless a global hardware reset,
* hardware initialization is needed to put those registers into an
* expected initial state.
*/
static void
-i40e_hw_init(struct i40e_hw *hw)
+i40e_hw_init(struct rte_eth_dev *dev)
{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+ i40e_enable_extended_tag(dev);
+
/* clear the PF Queue Filter control register */
I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
return 0;
}
-static int
-i40e_timesync_enable(struct rte_eth_dev *dev)
+static uint64_t
+i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_eth_link *link = &dev->data->dev_link;
- uint32_t tsync_ctl_l;
- uint32_t tsync_ctl_h;
+ uint64_t systim_cycles;
+
+ systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
+ systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
+ << 32;
+
+ return systim_cycles;
+}
+
+static uint64_t
+i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t rx_tstamp;
+
+ rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
+ rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
+ << 32;
+
+ return rx_tstamp;
+}
+
+static uint64_t
+i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint64_t tx_tstamp;
+
+ tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
+ tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
+ << 32;
+
+ return tx_tstamp;
+}
+
+static void
+i40e_start_timecounters(struct rte_eth_dev *dev)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+ struct rte_eth_link link;
uint32_t tsync_inc_l;
uint32_t tsync_inc_h;
- switch (link->link_speed) {
+ /* Get current link speed. */
+ memset(&link, 0, sizeof(link));
+ i40e_dev_link_update(dev, 1);
+ rte_i40e_dev_atomic_read_link_status(dev, &link);
+
+ switch (link.link_speed) {
case ETH_LINK_SPEED_40G:
tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
tsync_inc_h = 0x0;
}
- /* Clear timesync registers. */
- I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
- I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
- I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
- I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
-
/* Set the timesync increment value. */
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
+ memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
+ memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
+ memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
+
+ adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
+ adapter->systime_tc.cc_shift = 0;
+ adapter->systime_tc.nsec_mask = 0;
+
+ adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
+ adapter->rx_tstamp_tc.cc_shift = 0;
+ adapter->rx_tstamp_tc.nsec_mask = 0;
+
+ adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
+ adapter->tx_tstamp_tc.cc_shift = 0;
+ adapter->tx_tstamp_tc.nsec_mask = 0;
+}
+
+static int
+i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
+{
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
+ adapter->systime_tc.nsec += delta;
+ adapter->rx_tstamp_tc.nsec += delta;
+ adapter->tx_tstamp_tc.nsec += delta;
+
+ return 0;
+}
+
+static int
+i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
+{
+ uint64_t ns;
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
+ ns = rte_timespec_to_ns(ts);
+
+ /* Set the timecounters to a new value. */
+ adapter->systime_tc.nsec = ns;
+ adapter->rx_tstamp_tc.nsec = ns;
+ adapter->tx_tstamp_tc.nsec = ns;
+
+ return 0;
+}
+
+static int
+i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
+{
+ uint64_t ns, systime_cycles;
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
+ systime_cycles = i40e_read_systime_cyclecounter(dev);
+ ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
+ *ts = rte_ns_to_timespec(ns);
+
+ return 0;
+}
+
+static int
+i40e_timesync_enable(struct rte_eth_dev *dev)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ uint32_t tsync_ctl_l;
+ uint32_t tsync_ctl_h;
+
+ /* Stop the timesync system time. */
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
+ /* Reset the timesync system time value. */
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
+ I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
+
+ i40e_start_timecounters(dev);
+
+ /* Clear timesync registers. */
+ I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
+ I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
+ I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
+
/* Enable timestamping of PTP packets. */
tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
- /* Set the timesync increment value. */
+ /* Reset the timesync increment value. */
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
struct timespec *timestamp, uint32_t flags)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
uint32_t sync_status;
- uint32_t rx_stmpl;
- uint32_t rx_stmph;
uint32_t index = flags & 0x03;
+ uint64_t rx_tstamp_cycles;
+ uint64_t ns;
sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
if ((sync_status & (1 << index)) == 0)
return -EINVAL;
- rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
- rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
-
- timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
- timestamp->tv_nsec = 0;
+ rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
+ ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
+ *timestamp = rte_ns_to_timespec(ns);
- return 0;
+ return 0;
}
static int
struct timespec *timestamp)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct i40e_adapter *adapter =
+ (struct i40e_adapter *)dev->data->dev_private;
+
uint32_t sync_status;
- uint32_t tx_stmpl;
- uint32_t tx_stmph;
+ uint64_t tx_tstamp_cycles;
+ uint64_t ns;
sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
return -EINVAL;
- tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
- tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
+ tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
+ ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
+ *timestamp = rte_ns_to_timespec(ns);
- timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
- timestamp->tv_nsec = 0;
-
- return 0;
+ return 0;
}
/*
return 0;
}
-/*
- * i40e_vsi_get_bw_info - Query VSI BW Information
- * @vsi: the VSI being queried
- *
- * Returns 0 on success, negative value on failure
- */
-static enum i40e_status_code
-i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
-{
- struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
- struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
- struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
- enum i40e_status_code ret;
- int i;
- uint32_t tc_bw_max;
-
- /* Get the VSI level BW configuration */
- ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
- if (ret) {
- PMD_INIT_LOG(ERR,
- "couldn't get PF vsi bw config, err %s aq_err %s\n",
- i40e_stat_str(hw, ret),
- i40e_aq_str(hw, hw->aq.asq_last_status));
- return ret;
- }
-
- /* Get the VSI level BW configuration per TC */
- ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
- NULL);
- if (ret) {
- PMD_INIT_LOG(ERR,
- "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
- i40e_stat_str(hw, ret),
- i40e_aq_str(hw, hw->aq.asq_last_status));
- return ret;
- }
-
- if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
- PMD_INIT_LOG(WARNING,
- "Enabled TCs mismatch from querying VSI BW info"
- " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
- bw_ets_config.tc_valid_bits);
- /* Still continuing */
- }
-
- vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
- vsi->bw_info.bw_max_quanta = bw_config.max_bw;
- tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
- (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
- for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
- vsi->bw_info.bw_ets_share_credits[i] =
- bw_ets_config.share_credits[i];
- vsi->bw_info.bw_ets_limit_credits[i] =
- rte_le_to_cpu_16(bw_ets_config.credits[i]);
- /* 3 bits out of 4 for each TC */
- vsi->bw_info.bw_ets_max_quanta[i] =
- (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
- PMD_INIT_LOG(DEBUG,
- "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
- __func__, vsi->seid, i, bw_config.qs_handles[i]);
- }
-
- return ret;
-}
static enum i40e_status_code
i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
vsi->info.mapping_flags = ctxt.info.mapping_flags;
vsi->info.valid_sections = 0;
- /* Update current VSI BW information */
- ret = i40e_vsi_get_bw_info(vsi);
+ /* query and update current VSI BW information */
+ ret = i40e_vsi_get_bw_config(vsi);
if (ret) {
PMD_INIT_LOG(ERR,
"Failed updating vsi bw info, err %s aq_err %s",
uint32_t val;
/* Use the FW API if FW > v4.4*/
- if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
+ if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
+ (hw->aq.fw_maj_ver >= 5))) {
PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
" to configure DCB");
return I40E_ERR_FIRMWARE_API_VERSION;
git.droids-corp.org / dpdk.git / blobdiff