net/i40e: fix flow director Rx resource defect

[dpdk.git] / drivers / net / i40e / i40e_ethdev.c

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index f8abd5b..ba9f8a9 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1057,7 +1057,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
                return 0;
        }
        i40e_set_default_ptype_table(dev);
-       i40e_set_default_pctype_table(dev);
        pci_dev = RTE_ETH_DEV_TO_PCI(dev);
        intr_handle = &pci_dev->intr_handle;
 
@@ -1103,6 +1102,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
                return ret;
        }
 
+       i40e_set_default_pctype_table(dev);
+
        /*
         * To work around the NVM issue, initialize registers
         * for packet type of QinQ by software.
@@ -2144,9 +2145,6 @@ i40e_dev_stop(struct rte_eth_dev *dev)
        /* reset hierarchy commit */
        pf->tm_conf.committed = false;
 
-       /* Remove all the queue region configuration */
-       i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
-
        hw->adapter_stopped = 1;
 }
 
@@ -8139,14 +8137,17 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,
                (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
 
        /*
-        * We work only with lowest 32 bits which is not correct, but to work
-        * properly the valid_bit_mask size should be increased up to 64 bits
-        * and this will brake ABI. This modification will be done in next
-        * release
+        * As i40e supports less than 64 flow types, only first 64 bits need to
+        * be checked.
         */
-       g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
+       for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
+               g_cfg->valid_bit_mask[i] = 0ULL;
+               g_cfg->sym_hash_enable_mask[i] = 0ULL;
+       }
 
-       for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
+       g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
+
+       for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
                if (!adapter->pctypes_tbl[i])
                        continue;
                for (j = I40E_FILTER_PCTYPE_INVALID + 1;
@@ -8155,7 +8156,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw,
                                reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
                                if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
                                        g_cfg->sym_hash_enable_mask[0] |=
-                                                               (1UL << i);
+                                                               (1ULL << i);
                                }
                        }
                }
@@ -8169,7 +8170,7 @@ i40e_hash_global_config_check(const struct i40e_adapter *adapter,
                              const struct rte_eth_hash_global_conf *g_cfg)
 {
        uint32_t i;
-       uint32_t mask0, i40e_mask = adapter->flow_types_mask;
+       uint64_t mask0, i40e_mask = adapter->flow_types_mask;
 
        if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
                g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
@@ -8180,7 +8181,7 @@ i40e_hash_global_config_check(const struct i40e_adapter *adapter,
        }
 
        /*
-        * As i40e supports less than 32 flow types, only first 32 bits need to
+        * As i40e supports less than 64 flow types, only first 64 bits need to
         * be checked.
         */
        mask0 = g_cfg->valid_bit_mask[0];
@@ -8216,23 +8217,20 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
        int ret;
        uint16_t i, j;
        uint32_t reg;
-       /*
-        * We work only with lowest 32 bits which is not correct, but to work
-        * properly the valid_bit_mask size should be increased up to 64 bits
-        * and this will brake ABI. This modification will be done in next
-        * release
-        */
-       uint32_t mask0 = g_cfg->valid_bit_mask[0] &
-                                       (uint32_t)adapter->flow_types_mask;
+       uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
 
        /* Check the input parameters */
        ret = i40e_hash_global_config_check(adapter, g_cfg);
        if (ret < 0)
                return ret;
 
-       for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
+       /*
+        * As i40e supports less than 64 flow types, only first 64 bits need to
+        * be configured.
+        */
+       for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
                if (mask0 & (1UL << i)) {
-                       reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
+                       reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
                                        I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
 
                        for (j = I40E_FILTER_PCTYPE_INVALID + 1;
@@ -11008,8 +11006,8 @@ static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
        }
        memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
 
-       /* Flags: 0x3 updates port address */
-       i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
+       i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
+                                 mac_addr->addr_bytes, NULL);
 }
 
 static int