#define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
/* 8th word of flex payload */
#define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
-
+/* all 8 words flex payload */
+#define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
#define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
#define I40E_TRANSLATE_INSET 0
struct rte_eth_udp_tunnel *udp_tunnel);
static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
struct rte_eth_udp_tunnel *udp_tunnel);
+static void i40e_filter_input_set_init(struct i40e_pf *pf);
static int i40e_ethertype_filter_set(struct i40e_pf *pf,
struct rte_eth_ethertype_filter *filter,
bool add);
static int i40e_get_eeprom(struct rte_eth_dev *dev,
struct rte_dev_eeprom_info *eeprom);
+static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
+ struct ether_addr *mac_addr);
+
static const struct rte_pci_id pci_id_i40e_map[] = {
#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "rte_pci_dev_ids.h"
.xstats_reset = i40e_dev_stats_reset,
.queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
.dev_infos_get = i40e_dev_info_get,
+ .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
.vlan_filter_set = i40e_vlan_filter_set,
.vlan_tpid_set = i40e_vlan_tpid_set,
.vlan_offload_set = i40e_vlan_offload_set,
.get_reg = i40e_get_regs,
.get_eeprom_length = i40e_get_eeprom_length,
.get_eeprom = i40e_get_eeprom,
+ .mac_addr_set = i40e_set_default_mac_addr,
};
/* store statistics names and its offset in stats structure */
*/
i40e_flex_payload_reg_init(hw);
+ /* Initialize the input set for filters (hash and fd) to default value */
+ i40e_filter_input_set_init(pf);
+
/* Initialize the parameters for adminq */
i40e_init_adminq_parameter(hw);
ret = i40e_init_adminq(hw);
pf->main_vsi->eth_stats.rx_discards;
stats->ierrors = ns->crc_errors +
ns->rx_length_errors + ns->rx_undersize +
- ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
- stats->imissed;
+ ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
*/
static const uint64_t valid_fdir_inset_table[] = {
[I40E_FILTER_PCTYPE_FRAG_IPV4] =
- I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
[I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
- I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
- I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
- I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
[I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
- I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_SCTP_VT,
[I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
- I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
[I40E_FILTER_PCTYPE_FRAG_IPV6] =
- I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
[I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
- I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
- I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
[I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
- I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
- I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
[I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
- I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_SCTP_VT,
[I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
- I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
- I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
[I40E_FILTER_PCTYPE_L2_PAYLOAD] =
- I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
+ I40E_INSET_LAST_ETHER_TYPE,
};
if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
return val;
}
-static uint8_t
+static int
i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
{
uint8_t i, idx = 0;
if (!inset || !mask || !nb_elem)
return 0;
- if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
- for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
- mask[i] = 0;
- return I40E_INSET_MASK_NUM_REG;
- }
for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
- if (idx >= nb_elem)
- break;
- if (inset & inset_mask_map[i].inset) {
+ if ((inset & inset_mask_map[i].inset) == inset_mask_map[i].inset) {
+ if (idx >= nb_elem) {
+ PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
+ return -EINVAL;
+ }
mask[idx] = inset_mask_map[i].mask;
idx++;
}
return idx;
}
-static uint64_t
-i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
- enum i40e_filter_pctype pctype)
-{
- uint64_t reg = 0;
-
- if (filter == RTE_ETH_FILTER_HASH) {
- reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
- reg <<= I40E_32_BIT_WIDTH;
- reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
- } else if (filter == RTE_ETH_FILTER_FDIR) {
- reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
- reg <<= I40E_32_BIT_WIDTH;
- reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
- }
-
- return reg;
-}
-
static void
i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
(uint32_t)i40e_read_rx_ctl(hw, addr));
}
-static int
-i40e_set_hash_inset_mask(struct i40e_hw *hw,
- enum i40e_filter_pctype pctype,
- enum rte_filter_input_set_op op,
- uint32_t *mask_reg,
- uint8_t num)
+static void
+i40e_filter_input_set_init(struct i40e_pf *pf)
{
- uint32_t reg;
- uint8_t i;
+ struct i40e_hw *hw = I40E_PF_TO_HW(pf);
+ enum i40e_filter_pctype pctype;
+ uint64_t input_set, inset_reg;
+ uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
+ int num, i;
- if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
- return -EINVAL;
+ for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+ pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
+ if (!I40E_VALID_PCTYPE(pctype))
+ continue;
+ input_set = i40e_get_default_input_set(pctype);
- if (op == RTE_ETH_INPUT_SET_SELECT) {
- for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
- i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
- 0);
- if (i >= num)
- continue;
+ num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+ I40E_INSET_MASK_NUM_REG);
+ if (num < 0)
+ return;
+ inset_reg = i40e_translate_input_set_reg(input_set);
+
+ i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
+ (uint32_t)(inset_reg & UINT32_MAX));
+ i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
+ (uint32_t)((inset_reg >>
+ I40E_32_BIT_WIDTH) & UINT32_MAX));
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
+ (uint32_t)(inset_reg & UINT32_MAX));
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
+ (uint32_t)((inset_reg >>
+ I40E_32_BIT_WIDTH) & UINT32_MAX));
+
+ for (i = 0; i < num; i++) {
+ i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
+ mask_reg[i]);
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
mask_reg[i]);
}
- } else if (op == RTE_ETH_INPUT_SET_ADD) {
- uint8_t j, count = 0;
-
- for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
- reg = i40e_read_rx_ctl(hw,
- I40E_GLQF_HASH_MSK(i, pctype));
- if (reg & I40E_GLQF_HASH_MSK_MASK_MASK)
- count++;
+ /*clear unused mask registers of the pctype */
+ for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
+ i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
+ 0);
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
+ 0);
}
- if (count + num > I40E_INSET_MASK_NUM_REG)
- return -EINVAL;
+ I40E_WRITE_FLUSH(hw);
- for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
- i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
- mask_reg[j]);
+ /* store the default input set */
+ pf->hash_input_set[pctype] = input_set;
+ pf->fdir.input_set[pctype] = input_set;
}
-
- return 0;
}
-static int
-i40e_set_fd_inset_mask(struct i40e_hw *hw,
- enum i40e_filter_pctype pctype,
- enum rte_filter_input_set_op op,
- uint32_t *mask_reg,
- uint8_t num)
+int
+i40e_hash_filter_inset_select(struct i40e_hw *hw,
+ struct rte_eth_input_set_conf *conf)
{
- uint32_t reg;
- uint8_t i;
+ struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
+ enum i40e_filter_pctype pctype;
+ uint64_t input_set, inset_reg = 0;
+ uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
+ int ret, i, num;
- if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
+ if (!conf) {
+ PMD_DRV_LOG(ERR, "Invalid pointer");
+ return -EFAULT;
+ }
+ if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
+ conf->op != RTE_ETH_INPUT_SET_ADD) {
+ PMD_DRV_LOG(ERR, "Unsupported input set operation");
return -EINVAL;
+ }
- if (op == RTE_ETH_INPUT_SET_SELECT) {
- for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- 0);
- if (i >= num)
- continue;
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- mask_reg[i]);
- }
- } else if (op == RTE_ETH_INPUT_SET_ADD) {
- uint8_t j, count = 0;
-
- for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
- reg = i40e_read_rx_ctl(hw,
- I40E_GLQF_FD_MSK(i, pctype));
- if (reg & I40E_GLQF_FD_MSK_MASK_MASK)
- count++;
- }
- if (count + num > I40E_INSET_MASK_NUM_REG)
- return -EINVAL;
+ pctype = i40e_flowtype_to_pctype(conf->flow_type);
+ if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
+ PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
+ conf->flow_type);
+ return -EINVAL;
+ }
- for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- mask_reg[j]);
+ ret = i40e_parse_input_set(&input_set, pctype, conf->field,
+ conf->inset_size);
+ if (ret) {
+ PMD_DRV_LOG(ERR, "Failed to parse input set");
+ return -EINVAL;
}
+ if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
+ input_set) != 0) {
+ PMD_DRV_LOG(ERR, "Invalid input set");
+ return -EINVAL;
+ }
+ if (conf->op == RTE_ETH_INPUT_SET_ADD) {
+ /* get inset value in register */
+ inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
+ inset_reg <<= I40E_32_BIT_WIDTH;
+ inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
+ input_set |= pf->hash_input_set[pctype];
+ }
+ num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+ I40E_INSET_MASK_NUM_REG);
+ if (num < 0)
+ return -EINVAL;
+
+ inset_reg |= i40e_translate_input_set_reg(input_set);
+
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
+ (uint32_t)(inset_reg & UINT32_MAX));
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
+ (uint32_t)((inset_reg >>
+ I40E_32_BIT_WIDTH) & UINT32_MAX));
+
+ for (i = 0; i < num; i++)
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
+ mask_reg[i]);
+ /*clear unused mask registers of the pctype */
+ for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
+ i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
+ 0);
+ I40E_WRITE_FLUSH(hw);
+ pf->hash_input_set[pctype] = input_set;
return 0;
}
int
-i40e_filter_inset_select(struct i40e_hw *hw,
- struct rte_eth_input_set_conf *conf,
- enum rte_filter_type filter)
+i40e_fdir_filter_inset_select(struct i40e_pf *pf,
+ struct rte_eth_input_set_conf *conf)
{
+ struct i40e_hw *hw = I40E_PF_TO_HW(pf);
enum i40e_filter_pctype pctype;
- uint64_t inset_reg = 0, input_set;
- uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
- uint8_t num;
- int ret;
+ uint64_t input_set, inset_reg = 0;
+ uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
+ int ret, i, num;
if (!hw || !conf) {
PMD_DRV_LOG(ERR, "Invalid pointer");
return -EFAULT;
}
+ if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
+ conf->op != RTE_ETH_INPUT_SET_ADD) {
+ PMD_DRV_LOG(ERR, "Unsupported input set operation");
+ return -EINVAL;
+ }
pctype = i40e_flowtype_to_pctype(conf->flow_type);
if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
conf->flow_type);
return -EINVAL;
}
- if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
- PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
- return -EINVAL;
- }
-
ret = i40e_parse_input_set(&input_set, pctype, conf->field,
conf->inset_size);
if (ret) {
PMD_DRV_LOG(ERR, "Failed to parse input set");
return -EINVAL;
}
- if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
+ if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
+ input_set) != 0) {
PMD_DRV_LOG(ERR, "Invalid input set");
return -EINVAL;
}
- if (conf->op == RTE_ETH_INPUT_SET_ADD) {
- inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
- } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
- PMD_DRV_LOG(ERR, "Unsupported input set operation");
- return -EINVAL;
- }
+ /* get inset value in register */
+ inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
+ inset_reg <<= I40E_32_BIT_WIDTH;
+ inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
+
+ /* Can not change the inset reg for flex payload for fdir,
+ * it is done by writing I40E_PRTQF_FD_FLXINSET
+ * in i40e_set_flex_mask_on_pctype.
+ */
+ if (conf->op == RTE_ETH_INPUT_SET_SELECT)
+ inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
+ else
+ input_set |= pf->fdir.input_set[pctype];
num = i40e_generate_inset_mask_reg(input_set, mask_reg,
I40E_INSET_MASK_NUM_REG);
- inset_reg |= i40e_translate_input_set_reg(input_set);
-
- if (filter == RTE_ETH_FILTER_HASH) {
- ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
- num);
- if (ret)
- return -EINVAL;
+ if (num < 0)
+ return -EINVAL;
- i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
- (uint32_t)(inset_reg & UINT32_MAX));
- i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
- (uint32_t)((inset_reg >>
- I40E_32_BIT_WIDTH) & UINT32_MAX));
- } else if (filter == RTE_ETH_FILTER_FDIR) {
- ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
- num);
- if (ret)
- return -EINVAL;
+ inset_reg |= i40e_translate_input_set_reg(input_set);
- i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
- (uint32_t)(inset_reg & UINT32_MAX));
- i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
- (uint32_t)((inset_reg >>
- I40E_32_BIT_WIDTH) & UINT32_MAX));
- } else {
- PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
- return -EINVAL;
- }
+ i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
+ (uint32_t)(inset_reg & UINT32_MAX));
+ i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
+ (uint32_t)((inset_reg >>
+ I40E_32_BIT_WIDTH) & UINT32_MAX));
+
+ for (i = 0; i < num; i++)
+ i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
+ mask_reg[i]);
+ /*clear unused mask registers of the pctype */
+ for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
+ i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
+ 0);
I40E_WRITE_FLUSH(hw);
+ pf->fdir.input_set[pctype] = input_set;
return 0;
}
&(info->info.global_conf));
break;
case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
- ret = i40e_filter_inset_select(hw,
- &(info->info.input_set_conf),
- RTE_ETH_FILTER_HASH);
+ ret = i40e_hash_filter_inset_select(hw,
+ &(info->info.input_set_conf));
break;
default:
return 0;
}
+
+static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
+ struct ether_addr *mac_addr)
+{
+ struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+ if (!is_valid_assigned_ether_addr(mac_addr)) {
+ PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
+ return;
+ }
+
+ /* Flags: 0x3 updates port address */
+ i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
+}
git.droids-corp.org / dpdk.git / blobdiff