i40e: support DCB mode

[dpdk.git] / drivers / net / i40e / i40e_ethdev.h

diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index baac4a0..0c9c78c 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -36,6 +36,8 @@
 
 #include <rte_eth_ctrl.h>
 
+#define I40E_VLAN_TAG_SIZE        4
+
 #define I40E_AQ_LEN               32
 #define I40E_AQ_BUF_SZ            4096
 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
@@ -89,6 +91,11 @@
 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
 #define I40E_48_BIT_MASK  RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
 
+/* Linux PF host with virtchnl version 1.1 */
+#define PF_IS_V11(vf) \
+       (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
+       ((vf)->version_minor == 1))
+
 /* index flex payload per layer */
 enum i40e_flxpld_layer_idx {
        I40E_FLXPLD_L2_IDX    = 0,
@@ -197,6 +204,19 @@ struct i40e_macvlan_filter {
        uint16_t vlan_id;
 };
 
+/* Bandwidth limit information */
+struct i40e_bw_info {
+       uint16_t bw_limit;      /* BW Limit (0 = disabled) */
+       uint8_t  bw_max_quanta; /* Max Quanta when BW limit is enabled */
+
+       /* Relative TC credits across VSIs */
+       uint8_t  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
+       /* TC BW limit credits within VSI */
+       uint8_t  bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
+       /* TC BW limit max quanta within VSI */
+       uint8_t  bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
+};
+
 /*
  * Structure that defines a VSI, associated with a adapter.
  */
@@ -242,6 +262,7 @@ struct i40e_vsi {
        uint16_t vsi_id;
        uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
        uint8_t enabled_tc; /* The traffic class enabled */
+       struct i40e_bw_info bw_info; /* VSI bandwidth information */
 };
 
 struct pool_entry {
@@ -279,6 +300,17 @@ struct i40e_pf_vf {
        uint16_t reset_cnt; /* Total vf reset times */
 };
 
+/*
+ * Structure to store private data for flow control.
+ */
+struct i40e_fc_conf {
+       uint16_t pause_time; /* Flow control pause timer */
+       /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
+       uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
+       /* FC low water  0-7 for pfc and 8 for lfc unit:kilobytes */
+       uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
+};
+
 /*
  * Structure to store private data for VMDQ instance
  */
@@ -323,6 +355,27 @@ struct i40e_fdir_info {
        struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
 };
 
+#define I40E_MIRROR_MAX_ENTRIES_PER_RULE   64
+#define I40E_MAX_MIRROR_RULES           64
+/*
+ * Mirror rule structure
+ */
+struct i40e_mirror_rule {
+       TAILQ_ENTRY(i40e_mirror_rule) rules;
+       uint8_t rule_type;
+       uint16_t index;          /* the sw index of mirror rule */
+       uint16_t id;             /* the rule id assigned by firmware */
+       uint16_t dst_vsi_seid;   /* destination vsi for this mirror rule. */
+       uint16_t num_entries;
+       /* the info stores depend on the rule type.
+           If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
+           If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
+        */
+       uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
+};
+
+TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
+
 /*
  * Structure to store private data specific for PF instance.
  */
@@ -362,6 +415,9 @@ struct i40e_pf {
        struct i40e_vmdq_info *vmdq;
 
        struct i40e_fdir_info fdir; /* flow director info */
+       struct i40e_fc_conf fc_conf; /* Flow control conf */
+       struct i40e_mirror_rule_list mirror_list;
+       uint16_t nb_mirror_rule;   /* The number of mirror rules */
 };
 
 enum pending_msg {
@@ -437,6 +493,12 @@ struct i40e_adapter {
                struct i40e_pf pf;
                struct i40e_vf vf;
        };
+
+       /* for vector PMD */
+       bool rx_bulk_alloc_allowed;
+       bool rx_vec_allowed;
+       bool tx_simple_allowed;
+       bool tx_vec_allowed;
 };
 
 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
@@ -538,6 +600,14 @@ i40e_init_adminq_parameter(struct i40e_hw *hw)
        hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
 }
 
+static inline int
+i40e_align_floor(int n)
+{
+       if (n == 0)
+               return 0;
+       return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
+}
+
 #define I40E_VALID_FLOW(flow_type) \
        ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
        (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \