net/mlx5: support Rx queue count API

[dpdk.git] / drivers / net / i40e / i40e_ethdev.h

diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 79bfc67..11ecfc3 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -28,6 +28,7 @@
 #define I40E_NUM_DESC_ALIGN       32
 #define I40E_BUF_SIZE_MIN         1024
 #define I40E_FRAME_SIZE_MAX       9728
+#define I40E_TSO_FRAME_SIZE_MAX   262144
 #define I40E_QUEUE_BASE_ADDR_UNIT 128
 /* number of VSIs and queue default setting */
 #define I40E_MAX_QP_NUM_PER_VF    16
@@ -184,7 +185,7 @@ enum i40e_flxpld_layer_idx {
 #define I40E_ITR_INDEX_NONE             3
 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
-#define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 8160 /* 8160 us */
+#define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
 /* Special FW support this floating VEB feature */
 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
@@ -1077,6 +1078,9 @@ struct i40e_adapter {
        uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
        uint64_t flow_types_mask;
        uint64_t pctypes_mask;
+
+       /* For devargs */
+       uint8_t use_latest_vec;
 };
 
 /**
@@ -1318,17 +1322,17 @@ i40e_align_floor(int n)
 }
 
 static inline uint16_t
-i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)
+i40e_calc_itr_interval(bool is_pf, bool is_multi_drv)
 {
-       if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
-               if (is_multi_drv) {
-                       interval = I40E_QUEUE_ITR_INTERVAL_MAX;
-               } else {
-                       if (is_pf)
-                               interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
-                       else
-                               interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
-               }
+       uint16_t interval = 0;
+
+       if (is_multi_drv) {
+               interval = I40E_QUEUE_ITR_INTERVAL_MAX;
+       } else {
+               if (is_pf)
+                       interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
+               else
+                       interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
        }
 
        /* Convert to hardware count, as writing each 1 represents 2 us */
@@ -1392,6 +1396,8 @@ i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)
        (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
        ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
        ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
-       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
+       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \
+       ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC))
 
 #endif /* _I40E_ETHDEV_H_ */