*/
#define I40E_GL_RXERR1_H(_i) (0x00318004 + ((_i) * 8))
-#define I40E_VLAN_TAG_SIZE 4
-
#define I40E_AQ_LEN 32
#define I40E_AQ_BUF_SZ 4096
/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
I40E_FLAG_RSS_AQ_CAPABLE)
#define I40E_RSS_OFFLOAD_ALL ( \
- ETH_RSS_FRAG_IPV4 | \
- ETH_RSS_NONFRAG_IPV4_TCP | \
- ETH_RSS_NONFRAG_IPV4_UDP | \
- ETH_RSS_NONFRAG_IPV4_SCTP | \
- ETH_RSS_NONFRAG_IPV4_OTHER | \
- ETH_RSS_FRAG_IPV6 | \
- ETH_RSS_NONFRAG_IPV6_TCP | \
- ETH_RSS_NONFRAG_IPV6_UDP | \
- ETH_RSS_NONFRAG_IPV6_SCTP | \
- ETH_RSS_NONFRAG_IPV6_OTHER | \
- ETH_RSS_L2_PAYLOAD)
+ RTE_ETH_RSS_FRAG_IPV4 | \
+ RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
+ RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
+ RTE_ETH_RSS_FRAG_IPV6 | \
+ RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
+ RTE_ETH_RSS_L2_PAYLOAD)
/* All bits of RSS hash enable for X722*/
#define I40E_RSS_HENA_ALL_X722 ( \
* Considering QinQ packet, the VLAN tag needs to be counted twice.
*/
#define I40E_ETH_OVERHEAD \
- (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
+ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2)
#define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD)
#define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK)
TAILQ_ENTRY(i40e_tunnel_filter) rules;
struct i40e_tunnel_filter_input input;
uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
- uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
+ uint16_t vf_id; /* VF id, available when is_to_vf is 1. */
uint16_t queue; /* Queue assigned to when match */
};
uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
uint16_t queue_id; /**< Queue assigned to if match. */
uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
- uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
+ uint16_t vf_id; /**< VF id, available when is_to_vf is 1. */
};
TAILQ_HEAD(i40e_flow_list, rte_flow);
uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
sizeof(uint32_t)]; /**< Hash key. */
- uint16_t queue[ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */
+ uint16_t queue[RTE_ETH_RSS_RETA_SIZE_512]; /**< Queues indices to use. */
bool symmetric_enable; /**< true, if enable symmetric */
uint64_t config_pctypes; /**< All PCTYPES with the flow */
/*
* If message statistics from a VF exceed the maximal limitation,
* the PF will ignore any new message from that VF for
- * 'ignor_second' time.
+ * 'ignore_second' time.
*/
uint32_t ignore_second;
};
};
/**
- * Strucute to store private data for each VF representor instance
+ * Structure to store private data for each VF representor instance
*/
struct i40e_vf_representor {
uint16_t switch_domain_id;
uint16_t vf_id;
/**< Virtual Function ID */
struct i40e_adapter *adapter;
- /**< Private data store of assocaiated physical function */
+ /**< Private data store of associated physical function */
struct i40e_eth_stats stats_offset;
/**< Zero-point of VF statistics*/
};