#define _I40E_ETHDEV_H_
#include <rte_eth_ctrl.h>
+#include <rte_time.h>
#define I40E_VLAN_TAG_SIZE 4
#define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
#define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
+/* Default queue interrupt throttling time in microseconds */
+#define I40E_ITR_INDEX_DEFAULT 0
+#define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
+#define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
+
struct i40e_adapter;
/**
struct i40e_vf vf;
};
- /* for vector PMD */
+ /* For vector PMD */
bool rx_bulk_alloc_allowed;
bool rx_vec_allowed;
bool tx_simple_allowed;
bool tx_vec_allowed;
+
+ /* For PTP */
+ struct rte_timecounter systime_tc;
+ struct rte_timecounter rx_tstamp_tc;
+ struct rte_timecounter tx_tstamp_tc;
};
int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
}
+static inline uint16_t
+i40e_calc_itr_interval(int16_t interval)
+{
+ if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
+ interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
+
+ /* Convert to hardware count, as writing each 1 represents 2 us */
+ return (interval / 2);
+}
+
#define I40E_VALID_FLOW(flow_type) \
((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \