net/vmxnet3: support MSI-X interrupt

[dpdk.git] / drivers / net / i40e / i40e_ethdev.h

diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index cd48471..cd6deab 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -90,8 +90,10 @@
        do {                                                            \
                uint32_t ori_val;                                       \
                struct rte_eth_dev *dev;                                \
+               struct rte_eth_dev_data *dev_data;                      \
                ori_val = I40E_READ_REG((hw), (reg));                   \
-               dev = ((struct i40e_adapter *)hw->back)->eth_dev;       \
+               dev_data = ((struct i40e_adapter *)hw->back)->pf.dev_data; \
+               dev = &rte_eth_devices[dev_data->port_id];              \
                I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw),              \
                                                     (reg)), (value));  \
                if (ori_val != value)                                   \
@@ -283,6 +285,7 @@ struct rte_flow {
  */
 #define I40E_ETH_OVERHEAD \
        (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
+#define I40E_ETH_MAX_LEN (RTE_ETHER_MTU + I40E_ETH_OVERHEAD)
 
 #define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK)
 #define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK)
@@ -630,6 +633,7 @@ struct i40e_fdir_flow_ext {
        uint8_t raw_id;
        uint8_t is_vf;   /* 1 for VF, 0 for port dev */
        uint16_t dst_id; /* VF ID, available when is_vf is 1*/
+       uint64_t input_set;
        bool inner_ip;   /* If there is inner ip */
        enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
        enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */
@@ -786,7 +790,7 @@ struct i40e_fdir_info {
        bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
        bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
 
-       bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
+       uint32_t flow_count[I40E_FILTER_PCTYPE_MAX];
 
        uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER];
 };
@@ -1283,7 +1287,6 @@ struct i40e_vf {
 struct i40e_adapter {
        /* Common for both PF and VF */
        struct i40e_hw hw;
-       struct rte_eth_dev *eth_dev;
 
        /* Specific for PF or VF */
        union {
@@ -1311,6 +1314,12 @@ struct i40e_adapter {
 
        /* For RSS reta table update */
        uint8_t rss_reta_updated;
+#ifdef RTE_ARCH_X86
+       bool rx_use_avx2;
+       bool rx_use_avx512;
+       bool tx_use_avx2;
+       bool tx_use_avx512;
+#endif
 };
 
 /**
@@ -1457,8 +1466,8 @@ void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,
                                             uint8_t enable);
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
                            enum rte_filter_type filter, uint64_t inset);
-int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
-                                uint8_t nb_elem);
+int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+                                uint32_t *mask, uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
 void i40e_check_write_global_reg(struct i40e_hw *hw,
@@ -1532,7 +1541,7 @@ i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
 #define I40E_VSI_TO_DEV_DATA(vsi) \
        (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
 #define I40E_VSI_TO_ETH_DEV(vsi) \
-       (((struct i40e_vsi *)vsi)->adapter->eth_dev)
+       (&rte_eth_devices[((struct i40e_vsi *)vsi)->adapter->pf.dev_data->port_id])
 
 /* I40E_PF_TO */
 #define I40E_PF_TO_HW(pf) \