net/mrvl: support jumbo frame

[dpdk.git] / drivers / net / i40e / i40e_ethdev_vf.c

diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index 919f8c7..111ac39 100644 (file)
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -1225,7 +1225,15 @@ i40evf_init_vf(struct rte_eth_dev *dev)
        if (hw->mac.type == I40E_MAC_X722_VF)
                vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
        vf->vsi.vsi_id = vf->vsi_res->vsi_id;
-       vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
+
+       switch (vf->vsi_res->vsi_type) {
+       case VIRTCHNL_VSI_SRIOV:
+               vf->vsi.type = I40E_VSI_SRIOV;
+               break;
+       default:
+               vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
+               break;
+       }
        vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
        vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 
@@ -1435,6 +1443,7 @@ i40evf_dev_init(struct rte_eth_dev *eth_dev)
                return 0;
        }
        i40e_set_default_ptype_table(eth_dev);
+       i40e_set_default_pctype_table(eth_dev);
        rte_eth_copy_pci_info(eth_dev, pci_dev);
        eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 
@@ -2170,7 +2179,7 @@ i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
        dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
        dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
        dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
-       dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
+       dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
        dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
        dev_info->rx_offload_capa =
                DEV_RX_OFFLOAD_VLAN_STRIP |
@@ -2490,7 +2499,7 @@ static int
 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
 {
        struct i40e_hw *hw = I40E_VF_TO_HW(vf);
-       uint64_t rss_hf, hena;
+       uint64_t hena;
        int ret;
 
        ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
@@ -2498,14 +2507,7 @@ i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
        if (ret)
                return ret;
 
-       rss_hf = rss_conf->rss_hf;
-       hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
-       hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
-       if (hw->mac.type == I40E_MAC_X722)
-               hena &= ~I40E_RSS_HENA_ALL_X722;
-       else
-               hena &= ~I40E_RSS_HENA_ALL;
-       hena |= i40e_config_hena(rss_hf, hw->mac.type);
+       hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
        i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
        i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
        I40EVF_WRITE_FLUSH(hw);
@@ -2517,16 +2519,9 @@ static void
 i40evf_disable_rss(struct i40e_vf *vf)
 {
        struct i40e_hw *hw = I40E_VF_TO_HW(vf);
-       uint64_t hena;
 
-       hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
-       hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
-       if (hw->mac.type == I40E_MAC_X722)
-               hena &= ~I40E_RSS_HENA_ALL_X722;
-       else
-               hena &= ~I40E_RSS_HENA_ALL;
-       i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
-       i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
+       i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
+       i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
        I40EVF_WRITE_FLUSH(hw);
 }
 
@@ -2555,7 +2550,7 @@ i40evf_config_rss(struct i40e_vf *vf)
        }
 
        rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
-       if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
+       if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
                i40evf_disable_rss(vf);
                PMD_DRV_LOG(DEBUG, "No hash flag is set");
                return 0;
@@ -2580,14 +2575,13 @@ i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 {
        struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
        struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-       uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
+       uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
        uint64_t hena;
 
        hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
        hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
-       if (!(hena & ((hw->mac.type == I40E_MAC_X722)
-                ? I40E_RSS_HENA_ALL_X722
-                : I40E_RSS_HENA_ALL))) { /* RSS disabled */
+
+       if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
                if (rss_hf != 0) /* Enable RSS */
                        return -EINVAL;
                return 0;
@@ -2613,7 +2607,7 @@ i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 
        hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
        hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
-       rss_conf->rss_hf = i40e_parse_hena(hena);
+       rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
 
        return 0;
 }