I40E_VFINT_DYN_CTL01,
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return;
}
I40E_VFINT_DYN_CTL01_INTENA_MASK |
I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
}
static inline void
if (!rte_intr_allow_others(intr_handle)) {
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return;
}
else
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
}
static int
(interval <<
I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
rte_intr_enable(&dev->pci_dev->intr_handle);
I40E_RX_VEC_START),
0);
- I40E_WRITE_FLUSH(hw);
+ I40EVF_WRITE_FLUSH(hw);
return 0;
}