{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
int qinq = dev->data->dev_conf.rxmode.offloads &
- DEV_RX_OFFLOAD_VLAN_EXTEND;
+ RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
uint64_t reg_r = 0;
uint16_t reg_id;
uint16_t tpid;
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM,
item,
- "Exceeds maxmial payload limit.");
+ "Exceeds maximal payload limit.");
return -rte_errno;
}
for (i = 0; i < raw_spec->length; i++) {
j = i + next_dst_off;
+ if (j >= RTE_ETH_FDIR_MAX_FLEXLEN ||
+ j >= I40E_FDIR_MAX_FLEX_LEN)
+ break;
filter->input.flow_ext.flexbytes[j] =
raw_spec->pattern[i];
filter->input.flow_ext.flex_mask[j] =
}
static uint16_t i40e_supported_tunnel_filter_types[] = {
- ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
- ETH_TUNNEL_FILTER_IVLAN,
- ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
- ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
- ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
- ETH_TUNNEL_FILTER_IMAC,
- ETH_TUNNEL_FILTER_IMAC,
+ RTE_ETH_TUNNEL_FILTER_IMAC | RTE_ETH_TUNNEL_FILTER_TENID |
+ RTE_ETH_TUNNEL_FILTER_IVLAN,
+ RTE_ETH_TUNNEL_FILTER_IMAC | RTE_ETH_TUNNEL_FILTER_IVLAN,
+ RTE_ETH_TUNNEL_FILTER_IMAC | RTE_ETH_TUNNEL_FILTER_TENID,
+ RTE_ETH_TUNNEL_FILTER_OMAC | RTE_ETH_TUNNEL_FILTER_TENID |
+ RTE_ETH_TUNNEL_FILTER_IMAC,
+ RTE_ETH_TUNNEL_FILTER_IMAC,
};
static int
rte_memcpy(&filter->outer_mac,
ð_spec->dst,
RTE_ETHER_ADDR_LEN);
- filter_type |= ETH_TUNNEL_FILTER_OMAC;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_OMAC;
} else {
rte_memcpy(&filter->inner_mac,
ð_spec->dst,
RTE_ETHER_ADDR_LEN);
- filter_type |= ETH_TUNNEL_FILTER_IMAC;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_IMAC;
}
}
break;
filter->inner_vlan =
rte_be_to_cpu_16(vlan_spec->tci) &
I40E_VLAN_TCI_MASK;
- filter_type |= ETH_TUNNEL_FILTER_IVLAN;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_IVLAN;
}
break;
case RTE_FLOW_ITEM_TYPE_IPV4:
vxlan_spec->vni, 3);
filter->tenant_id =
rte_be_to_cpu_32(tenant_id_be);
- filter_type |= ETH_TUNNEL_FILTER_TENID;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_TENID;
}
vxlan_flag = 1;
rte_memcpy(&filter->outer_mac,
ð_spec->dst,
RTE_ETHER_ADDR_LEN);
- filter_type |= ETH_TUNNEL_FILTER_OMAC;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_OMAC;
} else {
rte_memcpy(&filter->inner_mac,
ð_spec->dst,
RTE_ETHER_ADDR_LEN);
- filter_type |= ETH_TUNNEL_FILTER_IMAC;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_IMAC;
}
}
filter->inner_vlan =
rte_be_to_cpu_16(vlan_spec->tci) &
I40E_VLAN_TCI_MASK;
- filter_type |= ETH_TUNNEL_FILTER_IVLAN;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_IVLAN;
}
break;
case RTE_FLOW_ITEM_TYPE_IPV4:
nvgre_spec->tni, 3);
filter->tenant_id =
rte_be_to_cpu_32(tenant_id_be);
- filter_type |= ETH_TUNNEL_FILTER_TENID;
+ filter_type |= RTE_ETH_TUNNEL_FILTER_TENID;
}
nvgre_flag = 1;
static int
i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
{
- struct rte_eth_dev *dev = pf->adapter->eth_dev;
+ struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
struct i40e_fdir_info *fdir_info = &pf->fdir;
struct i40e_fdir_filter *fdir_filter;
enum i40e_filter_pctype pctype;
}
/* Delete FDIR flows in flow list. */
- TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
+ RTE_TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
TAILQ_REMOVE(&pf->flow_list, flow, node);
}
for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
- pf->fdir.inset_flag[pctype] = 0;
+ pf->fdir.flow_count[pctype] = 0;
pf->fdir.flex_mask_flag[pctype] = 0;
}
}
/* Delete ethertype flows in flow list. */
- TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
+ RTE_TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
TAILQ_REMOVE(&pf->flow_list, flow, node);
rte_free(flow);
}
/* Delete tunnel flows in flow list. */
- TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
+ RTE_TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
TAILQ_REMOVE(&pf->flow_list, flow, node);
rte_free(flow);