crypto/qat: support GMAC in GEN4 legacy mode

[dpdk.git] / drivers / net / i40e / i40e_rxtx.c

diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index ee19102..026cda9 100644 (file)
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -81,6 +81,18 @@
 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
                (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
 
+static int
+i40e_monitor_callback(const uint64_t value,
+               const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
+{
+       const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
+       /*
+        * we expect the DD bit to be set to 1 if this descriptor was already
+        * written to.
+        */
+       return (value & m) == m ? -1 : 0;
+}
+
 int
 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
 {
@@ -93,12 +105,8 @@ i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
        /* watch for changes in status bit */
        pmc->addr = &rxdp->wb.qword1.status_error_len;
 
-       /*
-        * we expect the DD bit to be set to 1 if this descriptor was already
-        * written to.
-        */
-       pmc->val = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
-       pmc->mask = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
+       /* comparison callback */
+       pmc->fn = i40e_monitor_callback;
 
        /* registers are 64-bit */
        pmc->size = sizeof(uint64_t);
@@ -452,7 +460,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
        uint16_t pkt_len;
        uint64_t qword1;
        uint32_t rx_status;
-       int32_t s[I40E_LOOK_AHEAD], nb_dd;
+       int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
        int32_t i, j, nb_rx = 0;
        uint64_t pkt_flags;
        uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
@@ -482,11 +490,22 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
                                        I40E_RXD_QW1_STATUS_SHIFT;
                }
 
-               rte_smp_rmb();
+               /* This barrier is to order loads of different words in the descriptor */
+               rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 
                /* Compute how many status bits were set */
-               for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
-                       nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
+               for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
+                       var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
+#ifdef RTE_ARCH_ARM
+                       /* For Arm platforms, only compute continuous status bits */
+                       if (var)
+                               nb_dd += 1;
+                       else
+                               break;
+#else
+                       nb_dd += var;
+#endif
+               }
 
                nb_rx += nb_dd;
 
@@ -3064,7 +3083,7 @@ i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
                return I40E_ERR_BAD_PTR;
        }
 
-       dev = pf->adapter->eth_dev;
+       dev = &rte_eth_devices[pf->dev_data->port_id];
 
        /* Allocate the TX queue data structure. */
        txq = rte_zmalloc_socket("i40e fdir tx queue",
@@ -3122,7 +3141,7 @@ i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
                return I40E_ERR_BAD_PTR;
        }
 
-       dev = pf->adapter->eth_dev;
+       dev = &rte_eth_devices[pf->dev_data->port_id];
 
        /* Allocate the RX queue data structure. */
        rxq = rte_zmalloc_socket("i40e fdir rx queue",