git.droids-corp.org / dpdk.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
net/i40e: support TSO on tunneling packet
[dpdk.git] / drivers / net / i40e / i40e_rxtx.c
diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index d3cfb98..2cb2e30 100644 (file)
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -779,33 +779,65 @@ i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 #endif
        return flags;
 }
+
+static inline void
+i40e_parse_tunneling_params(uint64_t ol_flags,
+                           union i40e_tx_offload tx_offload,
+                           uint32_t *cd_tunneling)
+{
+       /* EIPT: External (outer) IP header type */
+       if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
+               *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
+       else if (ol_flags & PKT_TX_OUTER_IPV4)
+               *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
+       else if (ol_flags & PKT_TX_OUTER_IPV6)
+               *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
+
+       /* EIPLEN: External (outer) IP header length, in DWords */
+       *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
+               I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
+
+       /* L4TUNT: L4 Tunneling Type */
+       switch (ol_flags & PKT_TX_TUNNEL_MASK) {
+       case PKT_TX_TUNNEL_IPIP:
+               /* for non UDP / GRE tunneling, set to 00b */
+               break;
+       case PKT_TX_TUNNEL_VXLAN:
+       case PKT_TX_TUNNEL_GENEVE:
+               *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
+               break;
+       case PKT_TX_TUNNEL_GRE:
+               *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
+               break;
+       default:
+               PMD_TX_LOG(ERR, "Tunnel type not supported\n");
+               return;
+       }
+
+       /* L4TUNLEN: L4 Tunneling Length, in Words
+        *
+        * We depend on app to set rte_mbuf.l2_len correctly.
+        * For IP in GRE it should be set to the length of the GRE
+        * header;
+        * for MAC in GRE or MAC in UDP it should be set to the length
+        * of the GRE or UDP headers plus the inner MAC up to including
+        * its last Ethertype.
+        */
+       *cd_tunneling |= (tx_offload.l2_len >> 1) <<
+               I40E_TXD_CTX_QW0_NATLEN_SHIFT;
+}
+
 static inline void
 i40e_txd_enable_checksum(uint64_t ol_flags,
                        uint32_t *td_cmd,
                        uint32_t *td_offset,
-                       union i40e_tx_offload tx_offload,
-                       uint32_t *cd_tunneling)
+                       union i40e_tx_offload tx_offload)
 {
-       /* UDP tunneling packet TX checksum offload */
-       if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
-
+       /* Set MACLEN */
+       if (ol_flags & PKT_TX_TUNNEL_MASK)
                *td_offset |= (tx_offload.outer_l2_len >> 1)
                                << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
-
-               if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
-                       *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
-               else if (ol_flags & PKT_TX_OUTER_IPV4)
-                       *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
-               else if (ol_flags & PKT_TX_OUTER_IPV6)
-                       *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
-
-               /* Now set the ctx descriptor fields */
-               *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
-                               I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
-                               (tx_offload.l2_len >> 1) <<
-                               I40E_TXD_CTX_QW0_NATLEN_SHIFT;
-
-       } else
+       else
                *td_offset |= (tx_offload.l2_len >> 1)
                        << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 
@@ -994,6 +1026,8 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
                                        I40E_RXD_QW1_STATUS_SHIFT;
                }
 
+               rte_smp_rmb();
+
                /* Compute how many status bits were set */
                for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
                        nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
@@ -1436,10 +1470,10 @@ i40e_recv_scattered_pkts(void *rx_queue,
                        i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
                        I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
                if (pkt_flags & PKT_RX_RSS_HASH)
-                       rxm->hash.rss =
+                       first_seg->hash.rss =
                                rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
                if (pkt_flags & PKT_RX_FDIR)
-                       pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
+                       pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 
 #ifdef RTE_LIBRTE_IEEE1588
                pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
@@ -1484,7 +1518,8 @@ i40e_calc_context_desc(uint64_t flags)
 {
        static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
                PKT_TX_TCP_SEG |
-               PKT_TX_QINQ_PKT;
+               PKT_TX_QINQ_PKT |
+               PKT_TX_TUNNEL_MASK;
 
 #ifdef RTE_LIBRTE_IEEE1588
        mask |= PKT_TX_IEEE1588_TMST;
@@ -1506,7 +1541,7 @@ i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
        }
 
        /**
-        * in case of tunneling packet, the outer_l2_len and
+        * in case of non tunneling packet, the outer_l2_len and
         * outer_l3_len must be 0.
         */
        hdr_len = tx_offload.outer_l2_len +
@@ -1623,12 +1658,15 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
                /* Always enable CRC offload insertion */
                td_cmd |= I40E_TX_DESC_CMD_ICRC;
 
-               /* Enable checksum offloading */
+               /* Fill in tunneling parameters if necessary */
                cd_tunneling_params = 0;
-               if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
-                       i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
-                               tx_offload, &cd_tunneling_params);
-               }
+               if (ol_flags & PKT_TX_TUNNEL_MASK)
+                       i40e_parse_tunneling_params(ol_flags, tx_offload,
+                                                   &cd_tunneling_params);
+               /* Enable checksum offloading */
+               if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
+                       i40e_txd_enable_checksum(ol_flags, &td_cmd,
+                                                &td_offset, tx_offload);
 
                if (nb_ctx) {
                        /* Setup TX context descriptor if required */
@@ -2948,11 +2986,15 @@ i40e_dev_clear_queues(struct rte_eth_dev *dev)
        PMD_INIT_FUNC_TRACE();
 
        for (i = 0; i < dev->data->nb_tx_queues; i++) {
+               if (!dev->data->tx_queues[i])
+                       continue;
                i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
                i40e_reset_tx_queue(dev->data->tx_queues[i]);
        }
 
        for (i = 0; i < dev->data->nb_rx_queues; i++) {
+               if (!dev->data->rx_queues[i])
+                       continue;
                i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
                i40e_reset_rx_queue(dev->data->rx_queues[i]);
        }
@@ -2966,12 +3008,16 @@ i40e_dev_free_queues(struct rte_eth_dev *dev)
        PMD_INIT_FUNC_TRACE();
 
        for (i = 0; i < dev->data->nb_rx_queues; i++) {
+               if (!dev->data->rx_queues[i])
+                       continue;
                i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
                dev->data->rx_queues[i] = NULL;
        }
        dev->data->nb_rx_queues = 0;
 
        for (i = 0; i < dev->data->nb_tx_queues; i++) {
+               if (!dev->data->tx_queues[i])
+                       continue;
                i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
                dev->data->tx_queues[i] = NULL;
        }
@@ -3154,7 +3200,7 @@ i40e_set_rx_function(struct rte_eth_dev *dev)
                                struct i40e_rx_queue *rxq =
                                        dev->data->rx_queues[i];
 
-                               if (i40e_rxq_vec_setup(rxq)) {
+                               if (rxq && i40e_rxq_vec_setup(rxq)) {
                                        ad->rx_vec_allowed = false;
                                        break;
                                }
@@ -3216,7 +3262,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev)
                for (i = 0; i < dev->data->nb_rx_queues; i++) {
                        struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
 
-                       rxq->rx_using_sse = rx_using_sse;
+                       if (rxq)
+                               rxq->rx_using_sse = rx_using_sse;
                }
        }
 }
@@ -3255,7 +3302,7 @@ i40e_set_tx_function(struct rte_eth_dev *dev)
                                struct i40e_tx_queue *txq =
                                        dev->data->tx_queues[i];
 
-                               if (i40e_txq_vec_setup(txq)) {
+                               if (txq && i40e_txq_vec_setup(txq)) {
                                        ad->tx_vec_allowed = false;
                                        break;
                                }
DPDK repo used for reviews