net/iavf: enable interrupt polling

[dpdk.git] / drivers / net / i40e / i40e_rxtx.c

diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index e518409..3eb8257 100644 (file)
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -81,6 +81,18 @@
 #define I40E_TX_OFFLOAD_SIMPLE_NOTSUP_MASK \
                (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_SIMPLE_SUP_MASK)
 
+static int
+i40e_monitor_callback(const uint64_t value,
+               const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
+{
+       const uint64_t m = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
+       /*
+        * we expect the DD bit to be set to 1 if this descriptor was already
+        * written to.
+        */
+       return (value & m) == m ? -1 : 0;
+}
+
 int
 i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
 {
@@ -93,12 +105,8 @@ i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
        /* watch for changes in status bit */
        pmc->addr = &rxdp->wb.qword1.status_error_len;
 
-       /*
-        * we expect the DD bit to be set to 1 if this descriptor was already
-        * written to.
-        */
-       pmc->val = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
-       pmc->mask = rte_cpu_to_le_64(1 << I40E_RX_DESC_STATUS_DD_SHIFT);
+       /* comparison callback */
+       pmc->fn = i40e_monitor_callback;
 
        /* registers are 64-bit */
        pmc->size = sizeof(uint64_t);
@@ -482,7 +490,8 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
                                        I40E_RXD_QW1_STATUS_SHIFT;
                }
 
-               rte_smp_rmb();
+               /* This barrier is to order loads of different words in the descriptor */
+               rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
 
                /* Compute how many status bits were set */
                for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
@@ -2581,6 +2590,10 @@ i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
        rxq->rx_tail = 0;
        rxq->nb_rx_hold = 0;
+
+       if (rxq->pkt_first_seg != NULL)
+               rte_pktmbuf_free(rxq->pkt_first_seg);
+
        rxq->pkt_first_seg = NULL;
        rxq->pkt_last_seg = NULL;
 
@@ -3215,10 +3228,10 @@ i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
        qinfo->conf.offloads = txq->offloads;
 }
 
+#ifdef RTE_ARCH_X86
 static inline bool
 get_avx_supported(bool request_avx512)
 {
-#ifdef RTE_ARCH_X86
        if (request_avx512) {
                if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
                rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
@@ -3242,12 +3255,10 @@ get_avx_supported(bool request_avx512)
                return false;
 #endif
        }
-#else
-       RTE_SET_USED(request_avx512);
-#endif /* RTE_ARCH_X86 */
 
        return false;
 }
+#endif /* RTE_ARCH_X86 */
 
 
 void __rte_cold