static int iavf_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addrs,
uint32_t mc_addrs_num);
+static int iavf_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *arg);
static const struct rte_pci_id pci_id_iavf_map[] = {
{ RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) },
.flow_ops_get = iavf_dev_flow_ops_get,
.tx_done_cleanup = iavf_dev_tx_done_cleanup,
.get_monitor_addr = iavf_get_monitor_addr,
+ .tm_ops_get = iavf_tm_ops_get,
};
+static int
+iavf_tm_ops_get(struct rte_eth_dev *dev __rte_unused,
+ void *arg)
+{
+ if (!arg)
+ return -EINVAL;
+
+ *(const void **)arg = &iavf_tm_ops;
+
+ return 0;
+}
+
static int
iavf_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addrs,
/* configure RSS key */
if (!rss_conf->rss_key) {
/* Calculate the default hash key */
- for (i = 0; i <= vf->vf_res->rss_key_size; i++)
+ for (i = 0; i < vf->vf_res->rss_key_size; i++)
vf->rss_key[i] = (uint8_t)rte_rand();
} else
rte_memcpy(vf->rss_key, rss_conf->rss_key,
dev->data->nb_tx_queues);
num_queue_pairs = vf->num_queue_pairs;
+ if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS)
+ if (iavf_get_qos_cap(adapter)) {
+ PMD_INIT_LOG(ERR, "Failed to get qos capability");
+ return -1;
+ }
+
if (iavf_init_queues(dev) != 0) {
PMD_DRV_LOG(ERR, "failed to do Queue init");
return -1;
PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
goto err_api;
}
+
if (iavf_get_vf_resource(adapter) != 0) {
PMD_INIT_LOG(ERR, "iavf_get_vf_config failed");
goto err_alloc;
}
}
+ if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS) {
+ bufsz = sizeof(struct virtchnl_qos_cap_list) +
+ IAVF_MAX_TRAFFIC_CLASS *
+ sizeof(struct virtchnl_qos_cap_elem);
+ vf->qos_cap = rte_zmalloc("qos_cap", bufsz, 0);
+ if (!vf->qos_cap) {
+ PMD_INIT_LOG(ERR, "unable to allocate qos_cap memory");
+ goto err_rss;
+ }
+ iavf_tm_conf_init(dev);
+ }
+
iavf_init_proto_xtr(dev);
return 0;
rte_free(vf->rss_key);
rte_free(vf->rss_lut);
err_alloc:
+ rte_free(vf->qos_cap);
rte_free(vf->vf_res);
vf->vsi_res = NULL;
err_api:
iavf_dev_interrupt_handler, dev);
iavf_disable_irq0(hw);
+ if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS)
+ iavf_tm_conf_uninit(dev);
+
if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
if (vf->rss_lut) {
rte_free(vf->rss_lut);
rte_free(vf->aq_resp);
vf->aq_resp = NULL;
- vf->vf_reset = false;
+ /*
+ * If the VF is reset via VFLR, the device will be knocked out of bus
+ * master mode, and the driver will fail to recover from the reset. Fix
+ * this by enabling bus mastering after every reset. In a non-VFLR case,
+ * the bus master bit will not be disabled, and this call will have no
+ * effect.
+ */
+ if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))
+ vf->vf_reset = false;
return ret;
}
iavf_drv_i40evf_selected(struct rte_devargs *devargs, uint16_t device_id)
{
struct rte_kvargs *kvlist;
- const char *key = "driver";
int ret = 0;
if (device_id != IAVF_DEV_ID_VF &&
if (kvlist == NULL)
return 0;
- if (!rte_kvargs_count(kvlist, key))
+ if (!rte_kvargs_count(kvlist, RTE_DEVARGS_KEY_DRIVER))
goto exit;
/* i40evf driver selected when there's a key-value pair:
* driver=i40evf
*/
- if (rte_kvargs_process(kvlist, key,
+ if (rte_kvargs_process(kvlist, RTE_DEVARGS_KEY_DRIVER,
iavf_drv_i40evf_check_handler, NULL) < 0)
goto exit;
RTE_PMD_REGISTER_PCI_TABLE(net_iavf, pci_id_iavf_map);
RTE_PMD_REGISTER_KMOD_DEP(net_iavf, "* igb_uio | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_iavf, "cap=dcf driver=i40evf");
-RTE_LOG_REGISTER(iavf_logtype_init, pmd.net.iavf.init, NOTICE);
-RTE_LOG_REGISTER(iavf_logtype_driver, pmd.net.iavf.driver, NOTICE);
+RTE_LOG_REGISTER_SUFFIX(iavf_logtype_init, init, NOTICE);
+RTE_LOG_REGISTER_SUFFIX(iavf_logtype_driver, driver, NOTICE);
#ifdef RTE_ETHDEV_DEBUG_RX
-RTE_LOG_REGISTER(iavf_logtype_rx, pmd.net.iavf.rx, DEBUG);
+RTE_LOG_REGISTER_SUFFIX(iavf_logtype_rx, rx, DEBUG);
#endif
#ifdef RTE_ETHDEV_DEBUG_TX
-RTE_LOG_REGISTER(iavf_logtype_tx, pmd.net.iavf.tx, DEBUG);
+RTE_LOG_REGISTER_SUFFIX(iavf_logtype_tx, tx, DEBUG);
#endif