rxdid_map[flex_type] : IAVF_RXDID_COMMS_OVS_1;
}
+static int
+iavf_monitor_callback(const uint64_t value,
+ const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
+{
+ const uint64_t m = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
+ /*
+ * we expect the DD bit to be set to 1 if this descriptor was already
+ * written to.
+ */
+ return (value & m) == m ? -1 : 0;
+}
+
int
iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
{
/* watch for changes in status bit */
pmc->addr = &rxdp->wb.qword1.status_error_len;
- /*
- * we expect the DD bit to be set to 1 if this descriptor was already
- * written to.
- */
- pmc->val = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
- pmc->mask = rte_cpu_to_le_64(1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
+ /* comparison callback */
+ pmc->fn = iavf_monitor_callback;
/* registers are 64-bit */
pmc->size = sizeof(uint64_t);
rxq->rx_tail = 0;
rxq->nb_rx_hold = 0;
+
+ if (rxq->pkt_first_seg != NULL)
+ rte_pktmbuf_free(rxq->pkt_first_seg);
+
rxq->pkt_first_seg = NULL;
rxq->pkt_last_seg = NULL;
rxq->rxrearm_nb = 0;
volatile union iavf_rx_desc *rxd;
struct rte_mbuf *mbuf = NULL;
uint64_t dma_addr;
- uint16_t i;
+ uint16_t i, j;
for (i = 0; i < rxq->nb_rx_desc; i++) {
mbuf = rte_mbuf_raw_alloc(rxq->mp);
if (unlikely(!mbuf)) {
+ for (j = 0; j < i; j++) {
+ rte_pktmbuf_free_seg(rxq->sw_ring[j]);
+ rxq->sw_ring[j] = NULL;
+ }
PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
return -ENOMEM;
}
/* Free memory if needed */
if (dev->data->rx_queues[queue_idx]) {
- iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
+ iavf_dev_rx_queue_release(dev, queue_idx);
dev->data->rx_queues[queue_idx] = NULL;
}
rxq->crc_len = 0;
len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
- rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
+ rxq->rx_buf_len = RTE_ALIGN_FLOOR(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
/* Allocate the software ring. */
len = nb_desc + IAVF_RX_MAX_BURST;
tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
- check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
+ if (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)
+ return -EINVAL;
/* Free memory if needed. */
if (dev->data->tx_queues[queue_idx]) {
- iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
+ iavf_dev_tx_queue_release(dev, queue_idx);
dev->data->tx_queues[queue_idx] = NULL;
}
ad->tx_vec_allowed = false;
}
+ if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
+ vf->tm_conf.committed) {
+ int tc;
+ for (tc = 0; tc < vf->qos_cap->num_elem; tc++) {
+ if (txq->queue_id >= vf->qtc_map[tc].start_queue_id &&
+ txq->queue_id < (vf->qtc_map[tc].start_queue_id +
+ vf->qtc_map[tc].queue_count))
+ break;
+ }
+ if (tc >= vf->qos_cap->num_elem) {
+ PMD_INIT_LOG(ERR, "Queue TC mapping is not correct");
+ return -EINVAL;
+ }
+ txq->tc = tc;
+ }
+
return 0;
}
else
err = iavf_switch_queue_lv(adapter, rx_queue_id, true, true);
- if (err)
+ if (err) {
+ release_rxq_mbufs(rxq);
PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
rx_queue_id);
- else
+ } else {
dev->data->rx_queue_state[rx_queue_id] =
RTE_ETH_QUEUE_STATE_STARTED;
+ }
return err;
}
}
void
-iavf_dev_rx_queue_release(void *rxq)
+iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
{
- struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
+ struct iavf_rx_queue *q = dev->data->rx_queues[qid];
if (!q)
return;
}
void
-iavf_dev_tx_queue_release(void *txq)
+iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
{
- struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
+ struct iavf_tx_queue *q = dev->data->tx_queues[qid];
if (!q)
return;
return nb_tx;
}
+/* Check if the packet with vlan user priority is transmitted in the
+ * correct queue.
+ */
+static int
+iavf_check_vlan_up2tc(struct iavf_tx_queue *txq, struct rte_mbuf *m)
+{
+ struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
+ struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
+ uint16_t up;
+
+ up = m->vlan_tci >> IAVF_VLAN_TAG_PCP_OFFSET;
+
+ if (!(vf->qos_cap->cap[txq->tc].tc_prio & BIT(up))) {
+ PMD_TX_LOG(ERR, "packet with vlan pcp %u cannot transmit in queue %u\n",
+ up, txq->queue_id);
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
/* TX prep functions */
uint16_t
iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
int i, ret;
uint64_t ol_flags;
struct rte_mbuf *m;
+ struct iavf_tx_queue *txq = tx_queue;
+ struct rte_eth_dev *dev = &rte_eth_devices[txq->port_id];
+ struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
for (i = 0; i < nb_pkts; i++) {
m = tx_pkts[i];
rte_errno = -ret;
return i;
}
+
+ if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_QOS &&
+ ol_flags & (PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN)) {
+ ret = iavf_check_vlan_up2tc(txq, m);
+ if (ret != 0) {
+ rte_errno = -ret;
+ return i;
+ }
+ }
}
return i;